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TRAPS AND INTERRUPTS
4. Reenable traps by setting FTE.
5. Set KNF in the
psr
to avoid reexecuting the instruction.
The trap handler should ignore the SE bit for faults on
tid, ptld,
tst,
pst,
and
ixtr
instruc-
tions when in single-instruction mode or when in dual-instruction mode and the compan-
ion instruction is not a multiplier or adder operation. The SE value is undefined in this
case.
The trap handler should process result exceptions as described below and reexecute the
instruction before processing source exceptions.
7.4.2 Result Exception Faults
The class of result exceptions includes any of the following conditions:
• Overflow. The absolute value of the rounded true result would exceed the largest
finite number in the destination format.
• Underflow (when FZ is clear). The absolute value of the rounded true result would
be smaller than the smallest finite number in the destination format.
• Inexact result (when TI is set). The result is not exactly representable in the destina-
tion format. For example, the fraction 1/3 cannot be precisely represented in binary
form. This exception occurs frequently and indicates that some (generally acceptable)
accuracy has been lost.
The point at which a result exception is reported depends upon whether pipelined
operations are being used:
• Scalar (nonpipelined) operations. Result exceptions are reported on the next
floating-point,
tst.x,
or
pst.x
(and sometimes
tid, ptld, ixtr)
instruction after the scalar
operation. The instructions
tid, ptld
and
ixtr
report result exceptions when the Idest of
these instructions overlap the Idest of the instruction that caused the exception. When
a trap occurs, the last stage of the affected unit contains the result of the scalar
operation. The result is also written to the register indicated by the RR field of
the
psr.
• Pipelined operations. Result exceptions are reported when the result is in the last
stage and the next floating-point,
tst.x
or
pst.x
(and sometimes
tid, ptld, ixtr)
instruc-
tion is executed. The instructions
tid, ptld
and
ixtr
report result exceptions when the
Idest
of these instructions overlap the Idest of the instruction that caused the excep-
tion. When a trap occurs, the pipeline is not advanced, and the last stage results (that
caused the trap) remain unchanged.
When no trap occurs (either because FTE is clear or because no exception occurred),
the pipeline is advanced normally by the new floating-point operation. The result-status
bits of the affected unit are undefined until the point that result exceptions are reported.
7-7
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