Intel i86W Manual page 19

CHAPTER 1
ARCHITECTURAL OVERVIEW
The Intel i860™ Microprocessor defines a complete architecture that balances integer,
floating point, and graphics performance. Target applications include engineering work-
stations, scientific computing, 3-D graphics workstations, and multiuser systems. Its par-
allel architecture achieves high throughput with RISe design techniques, pipelined
processing units, wide data paths, and large on-chip caches.
1.1 OVERVIEW
The i860 microprocessor supports more than just integer operations. The architecture
includes on a single chip:
• . Integer operations
• Floating-point operations
• Graphics operations
• Memory-management support
• Data and instruction caches
Having a data cache as an integral part of the architecture provides support for vector
operations. The data cache supports applications programs in the conventional manner,
without explicit programming. For vector operations, however, programmers can explic-
itly use the data cache as if it were a large block of vector registers.
To sustain high performance, the i860 microprocessor incorporates wide information
paths that include:
• 64-bit external data bus
• 128-bit on-chip data bus
• 64-bit on-chip instruction bus
Floating-point vector operations use all three busses.
The i860 microprocessor includes a RISe integer core processing unit with one-clock
instruction execution. The core unit processes conventional integer programs and pro-
vides complete support for standard operating systems, such as UNIX and OS/2. The
core unit also drives the graphics and floating point hardware.
The i860 microprocessor supports vector floating-point operations without special vector
instructions or vector registers. It accomplishes this by using the on-chip data cache and
a variety of parallel techniques that include:
• Pipelined instruction execution with delayed branch instructions to avoid breaks in
the pipeline.
• Instructions that automatically increment index registers so as to reduce the number
of instructions needed for vector processing.
1-1