Intel i86W Manual page 200

INSTRUCTION SET SUMMARY
br
lbroff .................................................................................. Branch
Direct Unconditionally
Execute one more sequential instruction.
Continue execution at br.x(lbroff).
bri
[isrclni] .......................................................................... Branch
Indirect Unconditionally
Execute one more sequential instruction
IF any trap bit in psr is set
THEN copy PU to U, PIM to 1M in
psr
clear trap bits
FI
IF DS is set and DIM is reset
THEN enter dual-instruction mode after executing one
instruction in single-instruction mode
ELSE IF DS is set and DIM is set
FI
THEN enter single-instruction mode after executing one
instruction in dual-instruction mode
ELSE IF
THEN
ELSE
FI
FI
DIM is set
enter dual-instruction mode
for next instruction pair
enter single-instruction mode
for next instructions pair
Continue execution at address in isrclni
(The original contents of isrclni is used even if the next instruction
modifies isrclni. Does not trap if isrclni is misaligned.)
bte
isrcls, isrc2, sbroff .................................................................................... Branch
If Equal
IF
isrcls
=
isrc2
THEN continue execution at br.x(sbroff)
FI
btne
isrcls, isrc2, sbroff ........................................................................... Branch
If Not Equal
IF
isrcls ~ isrc2
THEN continue execution at br.x(sbroff)
FI
call
lbroff ......................................................................................................... Subroutine
Call
rl
~
address of next sequential instruction
+
4
Execute one more sequential instruction
Continue execution at br.x(lbroff)
calli
[isrclni] .................................................................................... .Indirect
Subroutine Call
rl ~ address of next sequential instruction
+
4
Execute one more sequential instruction
Continue execution at address in isrclni
(The original contents of isrclni is used even if the next instruction
modifies isrclni. Does not trap if isrclni is misaligned. The
register isrclni must not be r1.)
A-4