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CORE INSTRUCTIONS
For best performance, observe the following guidelines:
1. The destination of a
fld
or
pfld
should not be referenced as a source operand in the
next two instructions.
2. A
fld
instruction should not directly follow a store instruction that is expected to hit
in the data cache. There is no performance impact for a
pfld
following a store
instruction.
3. A string of successive
pfld
instructions causes internal delays due the fact that the
bandwith of the i860 microprocessor bus is one transfer per two cycles.
The assembler must align the immediate address offsets used in loads to the same
boundary as the effective address, because the lower bits of the immediate offset are
used to encode operand length information.
5-7
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