Intel i86W Manual page 138

TRAPS AND INTERRUPTS
6. Executing an indirect branch to the resumption address, making sure that at least
one of the trap bits is set in the
psr.
Neither the indirect branch nor the following
instruction may be executed in dual-instruction mode.
7. Restoring the register that holds the resumption address. (This is executed before
the delayed indirect branch is completed.)
7.2.3.1 DETERMINING WHERE TO RESUME
To determine where to resume execution upon leaving the trap handler, examine the
instruction at address
fir -
4. If this instruction is not a delayed control instruction, then
execution resumes at the address in
fir.
If, on the other hand, the instruction at
fir -
4 is a delayed control instruction (i.e. one
that executes the next sequential instruction on branch taken), the normal action is to
resume at
fir -
4 so that the control instruction (which did not finish because of the
trap) is also reexecuted. If the instruction at
fir -
4 is a
bla
instruction, then srcl should
be subtracted from src2 before reexecuting.
The one variance from this strategy occurs when the instruction at
fir -
4 is a condi-
tional delayed branch (
be.t
or
bne.t),
the instruction at
fir
is a
pfgt, pfle,
or
pfeq,
and a
source exception has occurred. To implement the IEEE standard for unordered com-
pares, the trap handler may need to change the value of CC. In this case it cannot
resume at
fir :-
4, because the new value of CC might cause an incorrect branch.
Instead, the trap handler must interpret the conditional branch instruction and resume
at its target.
When examining
fir -
4, take care not to cause a page fault. If the location in
fir
is at the
beginning of a page, then fir -
4 is in the prior page. If the prior page is not present,
then examining
fir -
4 will cause a page fault. In this case, however, the instruction at
fir
- 4 could not have been a delayed control instruction; therefore it is not necessary to
examine
fir -
4. Note that, when determining whether the prior page is not present, it is
necessary to inspect both the page table and its page directory entry.
If the i860 microprocessor was in dual-instruction mode and execution is to resume at
fir
- 4, DS should be set and DIM cleared in the
psr.
Clearing DIM prevents the floating-
point instruction associated with the control instruction from being reexecuted. Setting
DS forces the processor back to dual-instruction mode after executing the control
instruction.
Every code section should begin with a
nop
instruction so that
fir -
4 is defined even in
case a trap occurs on the first real instruction of the code section. Furthermore, this
nop
should not be the target of any branch or call.
7-4