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CHAPTER 5
CORE INSTRUCTIONS
Core instructions include loads and stores of the integer, floating-point, and control
registers; arithmetic and logical operations on the 32-bit integer registers; control trans-
fers; and system control functions. All these instructions are executed by the core unit.
For register operands, the abbreviations that describe the operands are composed of two
parts. The first part describes the type of register:
c
One of the control registers
fir, psr, epsr, dirbase, db,
or
fsr
f
One of the floating-point registers:
fO
through
f31
One of the integer registers:
rO
through
r31
The second part identifies the field of the machine instruction into which the operand is
to be placed:
srcl
srclni
srcls
src2
dest
The first of the two source-register designators, which may be ei-
ther a register or a 16-bit immediate constant or address offset.
The immediate value is zero-extended for logical operations and is
sign-extended for add and subtract operations (including
addu
and
subu)
and for all addressing calculations.
Same as srcl except that no immediate constant or address offset
value is permitted.
Same as srcl except that the immediate constant is a 5-bit value
that is zero-extended to 32 bits.
The second of the two source-register designators.
The destination register designator.
Thus, the operand specifier isrc2, for example, means that an integer register is used and
that the encoding of that register must be placed in the src2 field of the machine
instruction.
Other (nonregister) operands are specified by a one-part abbreviation that represents
both the type of operand required and the instruction field into which the value of the
operand is placed:
#const
Ibroff
A 16-bit immediate constant or address offset that the i860™ mi-
croprocessor sign-extends to 32 bits when computing the effective
address.
A signed, 26-bit, immediate, relative branch offset.
5-1
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