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INSTRUCTION FORMAT AND ENCODING
REG-Format Opcodes
Id.x
st.x
ixfr
fld.x, fst.x
flush
pst.d
Id.c, st.c
bri
trap
bte, btne
pfld.y
addu, -s, subu, -s,
shl, shr
shrd
bla
shra
and(h)
andnot(h)
or(h)
xor(h)
L
Integer Length
o
-8 bits
Load Integer
Store Integer
Integer to F-P Reg Transfer
(reserved)
Load/Store F-P
Flush
Pixel Store
Load/Store Control Register
Branch Indirect
Trap
(Escape for F-P Unit)
(Escape for Core Unit)
Branch Equal or Not Equal
Pipelined F-P Load
(CTRL-Format Instructions)
Add/Subtract
Logical Shift
Double Shift
Branch LCC Set and Add
Arithmetic Shift
AND
ANDNOT
OR
XOR
(reserved)
1
-16 or 32 bits (selected by bit 0)
LS
Load/Store
o
-Load
1
-Store
SO
Signed/Ordinal
o
-Ordinal
1
-Signed
H
High
o
-and, or, andnot, xor
1
- andh, orh, andnoth, xorh
B-4
31
30
29
28
27
26
0
0
0
L
0
0
0
0
L
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
LS
0
0
1
1
0
0
0
1
1
1
0
0
1
1
LS
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
1
E
0
1
1
0
0
0
1
1
x
x
1
0
0
SO
AS
1
0
1
0
LR
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
1
1
0
0
H
1
1
0
1
H
1
1
1
0
H
1
1
1
1
H
1
1
x
x
1
AS
Add/Subtract
o
-Add
1
-Subtract
LR
Left/Right
o -
Left Shift
1
- Right Shift
E
Equal
o -
Branch on Not Equal
1
- Branch on Equal
Immediate
o -
src1 is register
1
- src1 is immediate
I
1
0
0
I
1
1
0
0
1
0
1
I
I
x
I
I
0
1
I
I
I
I
I
0
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