Intel i86W Manual page 129

63
I
co re-o p
FLOATING-POINT INSTRUCTIONS
31
op
d.
fp-op
.poop
.p-op
op
op
o
Temporary
Dual-Instruction Mode.
I
Figure 6-11. Dual-Instruction Mode Transitions (2 of 2)
240329i
The recommended floating-point NOP for dual-instruction mode is
shrd rO,rO,rO,
be-
cause this instruction does not affect the states of the floating-point pipelines. Even
though this is a core instruction, bit 9 is interpreted as the dual-instruction mode control
bit. In assembly language, this instruction is specified as
fnop
or
d.fnop.
Traps are not
reported on
fnop.
Because it is a core instruction,
d.fnop
cannot be used to initiate entry
into dual-instruction mode.
6.8.1 Core and Floating-Point Instruction Interaction
1. If one of the branch-an-condition instructions
bc or bnc is paired with a floating-
point compare, the branch tests the value of the condition code prior to the
compare.
2. If an
ixfr, fld,
or
pfld
loads the same register as a source operand in the floating-
point instruction, the floating-point instruction references the register value before
the load updates it.
3. An
fst
or
pst
that stores a register that is the destination register of the companion
pipelined floating-point operation will store the result of the companion operation.
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