Dynamically Reconfiguring Channel Blocks; Interacting With The Dynamic Reconfiguration Interface - Intel Stratix 10 User Manual

7.1. Dynamically Reconfiguring Channel Blocks

Table 51. Intel Stratix 10 Dynamic Reconfiguration Feature Support
Reconfiguration
Channel Reconfiguration

7.2. Interacting with the Dynamic Reconfiguration Interface

Each transceiver channel contains a reconfiguration interface shared with the PMA
Interface (PMAIF), PMA and Embedded Multi-die Interconnect Bridge (EMIB).
Additionally, there are six reconfiguration interfaces per E-Tile allowing access to the
six RS-FEC blocks.
The reconfiguration interface provides direct access to the programmable space of
each channel. Communication with the channel reconfiguration interface requires an
AVMM master. Because each channel has its own dedicated AVMM interface, you can
dynamically reconfigure channels either concurrently or sequentially, depending on
how the AVMM master is connected to the AVMM reconfiguration interface.
Figure 78. Reconfiguration Interface in Intel Stratix 10 Transceiver IP Cores
A Native PHY IP core instance can specify multiple channels. You can use a dedicated
reconfiguration interface for each channel or share a single reconfiguration interface
across multiple channels to perform dynamic reconfiguration.
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Intel Stratix 10 E-Tile Transceiver PHY User Guide
120
AVMM Master
Embedded Controller in FPGA
or External Processor on PCB
Note:
1. The Native PHY IP core, user reconfiguration logic (AVMM master), interfaces
with the hard registers and EMIB using the AVMM reconfiguration interface.
Features
PMA Analog Features such as:
• VOD
• Pre-emphasis
• Enable RX adaptation
Enable/disable RS-FEC. Read out RS-FEC statistics
Reconfigure between NRZ and PAM4 when in PMA direct mode
TX local clock dividers, reference clock
RX local clock dividers, reference clock
Clock output frequency
Native PHY IP Core
Ch0: AVMM
Reconfiguration
Interface (1)
Ch1: AVMM
Reconfiguration
Interface (1)
7. Dynamic Reconfiguration
UG-20056 | 2019.02.04
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