Reset Controller Bypass - Intel Stratix 10 User Manual

Figure 71. TX PMA Reconfiguration with Reset Controller in Manual Mode Timing
Waveform
tx_pma_ready
tx_reset_req
tx_reset_ack
tx_aib_reset
tx_transfer_ready
rsfec_reset
tx_rsfec_reset
tx_pmaif_reset
AVMM

6.5.3. Reset Controller Bypass

You can access the resets for the internal PMA interface, RS-FEC, and EMIB blocks
when you bypass the reset controller, much like when the reset controller is in manual
mode.
The TRS block in the reset controller, which prevents multiple transceivers from being
in reset at the same time is not implemented.
If you have multiple E-Tile Native PHY IP core instances on a single E-Tile, make sure
that you assert/deassert reset to a single transceiver channel in an E-Tile at a time.
For example, if you instantiate three E-Tile Native PHY IP cores with the following
configurations:
• Instance A with one transceiver channel with RS-FEC disabled and the reset
controller in automatic mode
• Instance B with four transceiver channels with RS-FEC enabled in aggregate mode
and the reset controller in manual mode
• Instance C with two transceiver channels with RS-FEC enabled in fractured mode
and the reset controller bypassed
If you want to reset instances A or B, you cannot assert/deassert reset signals on
instance C at the same time.
If you want to reset instance C, you cannot reset instance A or B. If you previously
asserted reset on instance A, ensure that
instance A. If you previously deasserted reset on instance A, ensure that
and
rx_ready
rx_reset_req
6.5.3.1. Reset Controller Bypass Ports
You can control the reset signals listed in the following table.
® ®
Intel Stratix 10 E-Tile Transceiver PHY User Guide
112
Min 100 ns
Min 100 ns
Reset and reconfigure PMA
using PMA attribute codes
are asserted on instance A. Do not assert the
on instance B.
6. Resetting Transceiver Channels
and
tx_ready rx_ready
tx_reset_req
UG-20056 | 2019.02.04
Min 100 ns
Min 100 ns
are deasserted on
tx_ready
or
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