Single 25 Gbps Pma Direct Channel (With Fec) Within A Single Fec Block; Single 10 Gbps Pma Direct Channel (Without Fec) - Intel Stratix 10 User Manual

4.2.1. Single 25 Gbps PMA Direct Channel (with FEC) Within a Single FEC
Block
Table 40.

Single 25 Gbps PMA Direct Channel (with FEC) Within a Single FEC Block

Configuration
Data Rate
25.78125 Gbps
For FIFO in Phase Compensation mode, connect half rate
that is, 25.78125 Gbps/64) to
other source for
with
tx_clkout
Figure 51. PMA Direct with FEC
25.78125Gbps

4.2.2. Single 10 Gbps PMA Direct Channel (without FEC)

Table 41. Single 10 Gbps PMA Direct Channel Configuration
Data Rate
10.3125 Gbps
For FIFO in Phase Compensation mode, connect half rate
to
tx_coreclkin
you use any other source for
tx_coreclkin
rx_clkout
® ®
Intel Stratix 10 E-Tile Transceiver PHY User Guide
90
TX and RX Double Width
Enabled
tx_coreclkin
, make sure
tx_coreclkin
.
E-Tile Native PHY IP
XCVR
TX PMA
FEC
Interface
XCVR
RX PMA FEC
Interface
Legend:
TX PMA generated parallel clock (line rate / PMA interface width)
TX PMA generated parallel clock div by 2
RX PMA generated parallel clock div by 2
RX PMA generated parallel clock (line rate / PMA interface width)
TX and RX Double Width
Enabled
and connect
rx_clkout
tx_coreclkin
and
rx_coreclkin
, respectively
PMA Interface
32 bits
tx_clkout
and
rx_coreclkin
tx_coreclkin
EMIB
/2
TX Core
E-Tile FIFO
FIFO
RX Core
E-Tile FIFO
FIFO
PMA Interface
20 bits
tx_clkout
(257.8125 MHz) to
/
rx_coreclkin
have 0 PPM difference with
4. Clock Network
UG-20056 | 2019.02.04
Core Interface
64 bits
(402.83 MHz,
. If you use any
has 0 PPM difference
Native PHY IP Core Interface
tx_clkout
402.83 MHz
/2
tx_coreclkin
TX Data
RX Data
rx_coreclkin
/2
rx_clkout
402.83 MHz
Core Interface
40 bits
(257.8125 MHz)
. If
rx_coreclkin
, make sure
and
tx_clkout
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