Rsfec_Lanes_Rx_Stat; Rsfec_Lanes_Rx_Hold - Intel Stratix 10 User Manual

9. Register Map
UG-20056 | 2019.02.04
Bit Name
Restarts the synchronization.
2 fec_3bad RX was locked (and aligned if RSFEC_CORE_CFG.frac = none) but 3 consecutive FEC
codewords could not be corrected.
Restarts the synchronization.
1 not_locked RX lane not locked.
Not locked to alignment/codeword markers (100GE/128GFC/25GE) or to FEC
codewords (32GFC).
One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.
0 sf Incoming signal fail (transceiver unable to lock to signal).
One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.

9.5.15. rsfec_lanes_rx_stat

RS-FEC combined lanes RX status
The reset values in this table represents register values after a reset has completed.
Bit Name
1 not_deskew All RX lanes locked but the alignment markers were not unique or the skew was too
large.
This is an event signal, so use .not_align above instead to determine the alignment
state.
Restarts the synchronization.
Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).
0 not_align RX lanes not aligned (state).
Incoming signal fail, RX lanes not all locked, alignment markers not unique or skew
too large.
Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).

9.5.16. rsfec_lanes_rx_hold

RS-FEC combined lanes RX hold status
The reset values in this table represents register values after a reset has completed.
Bit Name
1 not_deskew All RX lanes locked but the alignment markers were not unique or the skew was too
large.
This is an event signal, so use .not_align above instead to determine the alignment
state.
Restarts the synchronization.
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Description
Description
Description
Description
Description
Address Addressing Mode
0x180 32-bits
Address Addressing Mode
0x188 32-bits
® ®
Intel Stratix 10 E-Tile Transceiver PHY User Guide
SW Access Reset
HW Access
Protection
-
RW 0x0
RO
-
RW 0x0
RO
-
RW 0x0
RO
-
SW Access Reset
HW Access
Protection
RO 0x0
WO
-
RO 0x0
WO
-
SW Access Reset
HW Access
Protection
W1C 0x0
W1S
-
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