Device Configuration Pins - Intel Stratix 10 Configuration User Manual

2. Intel Stratix 10 Configuration Details
UG-S10CONFIG | 2018.11.02
AS (Normal mode)
SD/MMC x4/x8
(3)
JTAG only
Related Information
• Intel Stratix 10 GX and SX Device Family Pin Connection Guidelines
• POR Specifications in Intel Stratix 10 Device Datasheet

2.4.3. Device Configuration Pins

All configuration schemes use the same dedicated pins for the standard control signals
shown in
There are no dedicated pins for the following signals:
•
PR_REQUEST
•
PR_ERROR
•
PR_DONE
•
CvP_CONFDONE
•
SEU_ERROR
•
DIRECT_TO_FACTORY
You can use the unused SDM I/O pins for
SEU_ERROR
pins by specifying them in the Intel Quartus Prime software and connecting them to
the Partial Reconfiguration External Configuration Controller Intel Stratix 10 FPGA IP.
Table 5. Intel Stratix 10 Device Configuration Pins
Configuration Function
(4)
TCK
(4)
TDI
(4)
TMS
(4)
TDO
nSTATUS
nCONFIG
(5)
MSEL[2:0]
(2)
If you use AS Fast mode and are not concerned about 100 ms PCIe linkup, you must still ramp
the supply within 18 ms. This ramp-up requirement ensures that the AS x4 device
VCCIO_SDM
is within its operating voltage range when the Intel Stratix 10 device begins to access it.
(3)
JTAG configuration works with any MSEL settings, unless disabled for security.
(4)
The JTAG pins can access the HPS JTAG chain in Intel Stratix 10 SoC devices.
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Configuration Scheme
Intel Stratix 10 Configuration Timing Diagram
pins. You can only use GPIO for
Configuration Scheme
JTAG
JTAG
JTAG
JTAG
All schemes
All schemes
All schemes
on page 14.
,
CvP_CONFDONE DIRECT_TO_FACTROY
,
PR_REQUEST PR_ERROR
Direction
Input V
CCIO_SDM
Input V
CCIO_SDM
Input V
CCIO_SDM
Output V
CCIO_SDM
Output V
CCIO_SDM
Input V
CCIO_SDM
Input V
CCIO_SDM
Intel Stratix 10 Configuration User Guide
MSEL[2:0]
011
100
111
, and
, and
PR_DONE
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