Pma Parameters - Intel Stratix 10 User Manual

2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
UG-20056 | 2019.02.04
Parameter
Number of data channels
Enable RSFEC
Provide separate interface
for each channel
Enable datapath and
interface reconfiguration
Number of reference clock
inputs
Initial TX reference clock
input selection
Enable dedicated RX
reference clock input
Dedicated RX clock input
selection

2.2.2. PMA Parameters

You can specify values for the following types of PMA parameters:
TX PMA:
• TX PMA Options
• TX PMA Pre-equalization
• TX Clocking Options
RX PMA:
• RX PMA Options
• RX PMA Optional Ports
• RX Clocking Options
(2)
When you enable RS-FEC, the number of data channels is 1-4.
Send Feedback
Value
•
The default is TX/RX Duplex.
1-24 Specifies the number of transceiver channels you want to
implement. The default value is 1. The maximum value is
24.
On/Off Enables the RS-FEC functionality.
On/Off When selected, the Native PHY IP core presents separate
data, reset, and clock interfaces for each channel rather
than a wide bus.
On/Off Enables the ability to preconfigure and dynamically switch
between the RS-FEC enabled and disabled modes.
(2)
1-5 Specifies the desired number of reference clocks intended
for the transmitter AND/OR receiver. This allows for
dynamic clock source switching. Native PHY IP Core allows
up to five clock inputs out of the possible nine for dynamic
clock switching.
0 This indicates the starting clock input selection used for
this configuration when dynamically switching between
multiple clock inputs.
On/Off Option to assign dedicated reference clock for the receiver
instead of sharing it with the transmitter.
0-4 When you enable the Enable Receiver dedicated
reference clock input option, you can select the input
clock with this parameter.
Description
TX/RX Duplex: Specifies a single channel that supports
both transmission and reception.
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Intel Stratix 10 E-Tile Transceiver PHY User Guide
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