Clock Network; Reference Clock Pins - Intel Stratix 10 User Manual

UG-20056 | 2019.02.04
Send Feedback

4. Clock Network

The Intel Stratix 10 E-Tile transceivers are equipped with the following clock networks:
• Reference clock
• Core interface clock

4.1. Reference Clock Pins

There are nine LVPECL reference clock pins on every Intel Stratix 10 E-Tile. You can
configure the pins as either 2.5-V LVPECL compliant or 3.3-V LVPECL tolerant. There
are source terminations (RS1 and RS2, 50 Ω each) and load terminations (RL1 and
RL2, 250 Ω each), as well as built-in internal AC coupling for differential reference
clock input pairs. Intel recommends using the default setting, which is internal source
termination at 2.5 V. Carefully disable internal source termination only when you need
external termination at 3.3 V (or 2.5 V). For external termination and related
reference clock detailed requirements, refer to the Intel Stratix 10 GX, MX, TX, and SX
Device Family Pin Connection Guidelines.
The Intel Stratix 10 E-Tile transceiver reference clock input pin supports a frequency
range of 125 MHz to 700 MHz, but the reference clock network supports a maximum
frequency of 500 MHz. Whenever you configure a reference clock frequency of greater
than 500 MHz, the Divide by 2 block is automatically instantiated in the back end.
The hardware supports nine reference clocks pins, but the Native PHY IP core
parameter editor provides any five reference clocks for a given design implementation.
You select which five based on your board layout.
Figure 49. IO Pad Ring - Transceiver Reference Clock Input Pad
REFCLK
REFCLK_N
E-Tile completes the power-up configuration successfully as long as a valid reference
clock frequency, 125 MHz - 500 MHz (if the
MHz - 700 MHz (if the
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
RL1
RS1
RS2
PAD
C1
PAD_N
C2
Reference Clock Buffer
Divide by 2 is enabled), is available during device
refclk
RL2
+
Divide
by 2
–
Divide by 2 is disabled) or 250
refclk
Reference
Clock
Network
ISO
9001:2015
Registered