Instantiating The Transceiver Native Phy Ip - Intel Stratix 10 User Manual

Figure 107. Device and Pin Options Button
3. From the General category, select either 100 MHz OSC_CLK_1 pin, 125 MHz
OSC_CLK_1 pin, or 25 MHz OSC_CLK_1 pin in the Configuration clock
source field depending on your clock frequency's availability.
Figure 108. Configuration Clock Source Selection
B.4. Instantiating the Transceiver Native PHY IP
This procedure describes how to instantiate your Intel Stratix 10 E-Tile Transceiver
Native PHY IP core.
® ®
Intel Stratix 10 E-Tile Transceiver PHY User Guide
220
B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation
UG-20056 | 2019.02.04
Send Feedback