Using Efuses - Intel Stratix 10 User Manual

Device security
Hide thumbs Also See for Stratix 10:
Table of Contents

Advertisement

UG-S10SECURITY | 2019.05.10
Send Feedback

7. Using eFuses

eFuses store the security and other Intel Stratix 10 device information. Intel Stratix 10
devices have a total of 8192 eFuse bits organized in four equal banks. Each bank has
64 rows. Each row has 32 eFuse bits.
Figure 19.
eFuse Mapping
Table 4.
Owner Programmable eFuses
Bank
0
Intel FPGA public key hash
0
Intel FPGA public key cancellation
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
Row 0
Row 63
Row 0
Row 63
Row 0
Row 63
Row 0
Row 63
Description
Size (Bits)
Bank 0
32-bit word
32-bit word
32-bit word
Bank 1
32-bit word
32-bit word
32-bit word
Bank 2
32-bit word
32-bit word
32-bit word
Bank 3
32-bit word
32-bit word
32-bit word
Legal Values
384
96-bit hex
128
boolean
Comments
Read only. 32 fuses are available.
Read only. There are 4 redundant
cancellation bits associated with
each fuse. All 4 are programmed
when you cancel the corresponding
fuse.
continued...
ISO
9001:2015
Registered

Advertisement

Table of Contents
loading

Table of Contents