Manual Reset Mode - Intel Stratix 10 User Manual

6. Resetting Transceiver Channels
UG-20056 | 2019.02.04

6.5.2. Manual Reset Mode

In manual mode, all ports are exposed to provide flexible control. Follow the reset
sequence for RX and TX modes to send reset requests.
Note: The manual reset mode is required if fractured RS-FEC is used.
Table 47. Native PHY IP Ports With Manual Mode Enabled
Port
rx_reset_req
rx_reset_ack
rx_aib_reset
rx_pmaif_reset
rx_rsfec_reset
rx_transfer_ready
rx_pma_ready
rx_is_lockedtodata
tx_reset_req
tx_reset_ack
rsfec_reset
tx_aib_reset
tx_pmaif_reset
tx_rsfec_reset
tx_transfer_ready
tx_pma_ready
The
reset
Send Feedback
Direction
Input Request to Master TRS to schedule RX reset
Output
Valid window for you to assert/deassert
rx_rsfec_reset
Input Reset RX EMIB datapath
Input Reset RX PMA digital logic
Input Reset RX RS-FEC datapath
Output Output from the Native PHY IP core indicating the RX EMIB datapath is ready
Output Output from the PMA indicating the PMA is ready. This must be asserted before
asserting or deasserting any RX resets.
Output Output from the PMA indicating the CDR has locked to the incoming serial data
Input Request to Master TRS to schedule TX reset
Output
Valid window to assert or deassert
tx_rsfec_reset
Input Reset all RS-FEC logic
Input Reset TX EMIB datapath
Input Reset TX PMA digital logic
Input Reset TX RS-FEC datapath
Output Output from the Native PHY IP core indicating the TX EMIB datapath is ready
Output Output from the PMA indicating the PMA is ready. This must be asserted before
asserting or deasserting any TX resets.
, , and
rx_ready tx_ready
Description
rx_aib_reset
tx_aib_reset
,
rsfec_reset
ports do not appear in manual reset mode.
®
Intel Stratix
, ,
rx_pmaif_reset
, ,
tx_pmaif_reset
®
10 E-Tile Transceiver PHY User Guide
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