Table Of Contents - Intel Stratix 10 Configuration User Manual

Contents
® ®
1. Intel Stratix 10 Configuration Overview..................................................................... 4
®
1.1. Intel Stratix
1.1.1. Configuration and Related Signals................................................................ 7
1.1.2. Intel Download Cables Supporting Configuration in Intel Stratix 10 Devices....... 8
1.2. Intel Stratix 10 Configuration Architecture................................................................ 8
1.2.1. Secure Device Manager.............................................................................. 9
2. Intel Stratix 10 Configuration Details........................................................................... 12
2.1. Configuration Flow Diagram.................................................................................. 12
2.2. Intel Stratix 10 Configuration Timing Diagram......................................................... 14
2.3. Additional Clock Requirements for Transceivers, HPS, PCIe, High Bandwidth
Memory (HBM2) and SmartVID........................................................................... 16
2.4. Intel Stratix 10 Configuration Pins.......................................................................... 17
2.4.1. SDM Pin Mapping..................................................................................... 17
2.4.2. MSEL Settings......................................................................................... 18
2.4.3. Device Configuration Pins..........................................................................19
2.4.4. Setting Additional Configuration Pins.......................................................... 21
2.4.5. Enabling Dual-Purpose Pins....................................................................... 22
2.5. Setting Configuration Clock Source.........................................................................23
2.6. Configuration Clocks.............................................................................................24
2.6.1. OSC_CLK_1 Clock Input............................................................................24
2.7. Configuration and Programming Files......................................................................25
3. Intel Stratix 10 Configuration Schemes........................................................................ 27
3.1. Avalon-ST Configuration....................................................................................... 27
3.1.1. Enabling Avalon-ST Device Configuration.....................................................28
3.1.2. Avalon-ST Configuration Timing................................................................. 28
3.1.3. Avalon-ST Single-Device Configuration........................................................30
3.1.4. RBF Configuration File Format....................................................................32
3.1.5. Debugging Guidelines for the Avalon-ST Configuration Scheme...................... 33
3.1.6. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel
Flash Loader II IP Core............................................................................. 34
3.2. AS Configuration..................................................................................................51
3.2.1. AS Single-Device Configuration.................................................................. 51
3.2.2. AS Using Multiple Serial Flash Devices........................................................ 52
3.2.3. AS Configuration Timing........................................................................... 53
3.2.4. Programming Serial Flash Devices.............................................................. 54
3.2.5. Serial Flash Memory Layout.......................................................................56
3.2.6. AS_CLK.................................................................................................. 57
3.2.7. Active Serial Configuration Software Settings...............................................58
3.2.8. Generating and Programming AS Configuration Programming Files................. 59
3.2.9. Debugging Guidelines for the AS Configuration Scheme.................................61
3.3. Configuration from SD MMC.................................................................................. 62
3.3.1. SD MMC Single-Device Configuration.......................................................... 62
3.4. JTAG Configuration...............................................................................................63
3.4.1. JTAG Single-Device Configuration...............................................................64
3.4.2. JTAG Multi-Device Configuration.................................................................66
3.4.3. Debugging Guidelines for the JTAG Configuration Scheme............................. 67
Intel Stratix 10 Configuration User Guide
2
®
10 Configuration Overview................................................................ 4
Contents
Send Feedback