Rsfec_Err_Inj_Tx; Rsfec_Err_Val_Tx - Intel Stratix 10 User Manual

Bit Name
Should not become set. One bit per SRAM.
Bits 0-3 covers the deskew buffers for physical lanes 0-3 (only used when
RSFEC_CORE_CFG.frac = none).
Bits 4-7 covers the data buffers for the RS decoding. When RSFEC_CORE_CFG.frac =
frac4, these are used 1:1 for the physical lanes 0-3.

9.5.22. rsfec_err_inj_tx

Register Name
rsfec_err_inj_tx_0
rsfec_err_inj_tx_1
rsfec_err_inj_tx_2
rsfec_err_inj_tx_3
The reset values in this table represents register values after a reset has completed.
Bit Name
15:8 pat TX error injection pattern for each lane.
Value specifies which bits are being toggled on each lane, when that lane is hit. There
is an 8b pattern per lane. When a 66b word on a lane is hit, 8 consecutive bits out of
these 66 are XOR'ed with the pattern.
One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.
7:0 rate TX error injection rate for each physical lane.
Data is output towards the PMA 66 bits at a time (not to be confused with 66b PCS
symbols). The value specifies the fraction of such 66b words to hit. The unit is 1/256th
so a value of, say, 7 causes 7/256th of the 66b words being sent on the lane to be hit.
One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.

9.5.23. rsfec_err_val_tx

Register Name
rsfec_err_val_tx_0
rsfec_err_val_tx_1
rsfec_err_val_tx_2
rsfec_err_val_tx_3
The reset values in this table represents register values after a reset has completed.
Bit Name
15:8 inj1s Same for bits changed from 0 to 1 on each physical lane.
® ®
Intel Stratix 10 E-Tile Transceiver PHY User Guide
206
Description
Description
RS-FEC error injection mode
Description
Description
RS-FEC per lane error injection status
Description
UG-20056 | 2019.02.04
Address Addressing Mode
0x1E0 32-bits
0x1E4
0x1E8
0x1EC
Address Addressing Mode
0x1F0 32-bits
0x1F4
0x1F8
0x1FC
9. Register Map
SW Access Reset
HW Access
Protection
WO1S
-
SW Access Reset
HW Access
Protection
RW 0x00
RO
-
RW 0x00
RO
-
SW Access Reset
HW Access
Protection
RO 0x00
WO
continued...
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