0X0008: Internal Or Serial Loopback And Reverse Parallel Loopback Control - Intel Stratix 10 User Manual

Description
Configures RX of transceiver channel to the appropriate divide-by ratio. See Supported
Data Rate Ratios for PMA Attribute Codes 0x0005 and 0x0006 for valid settings.
• 0x84[7:0] Set the data rate to reference clock frequency ratio
• 0x85[2:0]: 3'b000 to set the RX running at more than 15 Gbaud per second
• 0x85[2:0]: 3'b001 to set the RX running at half rate
• 0x85[2:0]: 3'b010 to set the RX running at quarter rate
• 0x85[2:0]: 3'b011 to set the RX running at one-eighth rate
• 0x85[3]: 3'h0
•
0x85[6]: 1'b0 to select
•
0x85[6]: 1'b1 to select
• 0x85[7]: 1'b1 to apply settings to both TX and RX
PMA Can Be Running While Updating PMA Attribute?
No
Return Value {0x89[7:0],0x88[7:0]}
0x00FF: Invalid configuration
0x0006: Success
Related Information
Supported Data Rate Ratios for PMA Attribute Codes 0x0005 and 0x0006
9.2.6. 0x0008: Internal or Serial Loopback and Reverse Parallel Loopback
Control
Attribute Code
0x0008
Description
Controls turning on/off internal or serial loopback or reverse parallel loopback.
• 0x84[0]: 1'b1 to select internal or serial loopback. 1'b0 to disable internal or serial
loopback.
• 0x84[3:1]: 3'h0
• 0x84[4]: 1'b1 to select reverse parallel loopback. 1'b0 to disable reverse parallel
loopback.
• 0x84[7:5]: 3'h0
• 0x85[0]: 1'b1 to change the internal or serial loopback settings
• 0x85[1]: 1'b1 to set the reverse parallel loopback settings
• 0x85[7:2]: 6'h00
® ®
Intel Stratix 10 E-Tile Transceiver PHY User Guide
174
as the RX reference clock
refclk_in_a
as the RX reference clock
refclk_in_b
9. Register Map
UG-20056 | 2019.02.04
on page 187
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