Rs-Fec Registers - Intel Stratix 10 User Manual

Ratio
146
148
150
152
154
155
156
158
160
162
164
165
166
168
170
172
174
175
176
178
180

9.5. RS-FEC Registers

The delay between RS-FEC register reads should be at least 10 μs.
Table 63. RS-FEC Registers
Address Name
0x04 rsfec_top_clk_cfg
0x10 rsfec_top_tx_cfg
0x14 rsfec_top_rx_cfg
0x20 tx_aib_dsk_conf
0x30 rsfec_core_cfg
0x40 rsfec_lane_cfg_0
0x44 rsfec_lane_cfg_1
0x48 rsfec_lane_cfg_2
0x4C rsfec_lane_cfg_3
® ®
Intel Stratix 10 E-Tile Transceiver PHY User Guide
190
Supported Above 15
Gbaud per Second
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RS-FEC Clock configuration register
RS-FEC TX configuration register
RS-FEC RX configuration register
Defines the configuration fields for TX Deskew
RS-FEC core configuration
RS-FEC per lane configuration
1/2 Rate 1/4 Rate
Yes No
Yes Yes
Yes No
Yes Yes
Yes No
No No
Yes Yes
Yes No
Yes Yes
Yes No
Yes Yes
No No
Yes No
Yes Yes
Yes No
Yes Yes
Yes No
No No
Yes Yes
Yes No
Yes Yes
Description
9. Register Map
UG-20056 | 2019.02.04
1/8 Rate
No
No
No
Yes
No
No
No
No
Yes
No
No
No
No
Yes
No
No
No
No
Yes
No
No
Reset
0x0000 0F00
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
continued...
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