Processor Core; Geodelink Interface Units; Geodelink Memory Controller - Micros Systems Workstation 4 LX Service Manual

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WS4 LX Technical Overview
LX800 Processor and TFT Controller

Processor Core

The processor core consists of an integer unit, cache memory subsystem, and an x87
compatible floating point unit. The integer unit contains the instruction pipelines and
associated logic. The memory subsystem contains the instruction and data caches,
translation look-aside buffers (TLBs) and an interface to the GeodeLink Interface
Units (GLIUs).
The LX800 instruction set is based on a combination of Intel's Pentium
®
K6
processor, and the Athlon
processor specific instructions.

GeodeLink Interface Units

The pair of GeodeLink Interface Units (GLIU0 and GLIU1 in the LX800 block
diagram, Figure 4-2) form the heart of GeodeLink architecture. Each features a
built-in arbiter that enables dynamic allocation of memory bandwidth, with on-the-fly
prioritization.
Internally each GLIU includes seven channels, with channel 0 reserved for the GLIU
itself and not considered a physical port. Together, GLIU0 and GLIU1 make up the
internal bus comprised of the GeodeLink architecture. GLIU0 connects to the five
modules that require high bandwidth, and GLIU1 connects to the five low bandwidth
modules.
GLIU0 is connected to modules with high-bandwidth requirements:
CPU Core
GeodeLink Memory Controller (GLMC)
Graphics Processor
Display Controller
GLIU1 (GeodeLink Interface Unit 1).
GLIU1 is connected to modules with lower bandwidth requirements:
GeodeLink Control Processor (GLCP)
Video Input Port
GeodeLink PCI Bridge
TFT Controller/Video Output Port (VOP)
Security Block.

GeodeLink Memory Controller

The GeodeLink Memory Controller provides all of the LX800 memory needs. The
GLMC is capable of handling multiple requests for memory data from the CPU core,
the Graphics Processor, the Display Controller and the external PCI bus via the
GeodeLink Interface Units (GLIUs). Contention for memory bandwidth between the
various modules is minimized by extensive buffering logic.
Because the GLMC supports the memory requirements of both the CPU core and
display sub-system, it is classified as a Unified Memory Architecture (UMA)
subsystem.
4-4
Floating point unit, and the AMD Geode
Workstation 4 and 4 LX Field Service Guide
®
, the AMD
LX

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