Xerox Phaser 6100 Service Manual page 39

Flash Memory
4MB
5 pin UART
Panel
16x2 LCD
1) CPU BLOCK
A 120MHz - 32bit RISC processor is used to manage commands and data supplied by the host. This is converted
into a bitmap image which is passed to the engine block for printing.
2) SPGPm (Samsung Printer Graphics Processor) overview
Package: 272 pins PBGA
Power: 1.8V(Core), 3.3V(IO) power operation, P1284 inputs : 5V tolerant
Speed: 120MHz core ( ARM946ES) operation, 60MHz bus operation,
supportable engine speed: under 30ppm
Dual bus architecture for bus traffic distribution:
AMBA High performance Bus (AHB)
System Bus with SDRAM
Integrated ARM946ES: 32-bit RISC embedded processor core
Direct connection up to 5 SDRAM arrays:
SDRAM controller supports PC-66, PC-100 and PC-133 SDRAMs running at 60MHz
Up to 128MB per array, up to 512MB totally
Wide supports for various SDRAM configurations, including programmable band and column address
Programmable SDRAM refresh time interval
IEEE1284 compliant parallel port interface
Compatible ECP communications are supported
Direct support for IEEE1284 compliant data transceivers
High performance DMA based Interface to Printer Engine
Engine Controller
Motor Control Unit: Motor Speed Lookup Table Memory (128 x 16 x 2)
Pulse Width Modulation Unit
ADC Interface Unit
LSU Interface Unit
Ethernet Controller (MAC)
Full compliance with IEEE standard 802.3, 802.3u specification
Support 10/100 Mbps data transfer rates
(W-LAN)
NOT SUPPORTED
SPGPm
EEPROM
2048 bytes
SDRAM
64MB
SDRAM DIMM
34MB~128MB
USB 2.0
Service Manual 4-11
Summary of Product
LPEC1
Engine
Control
Bloc k