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by
the access control image.
MMC moves the access con-
trol image into the access control registers one word at a
ti me, thus loading th2 controls for 16 consecutive 512-word
pages with each image word.
As each word is loaded, the
virtual address of the control image is incremented by 1,
the word count is decremented by 1, and the value in bit
positions 15-20 of register Ru1 is incremented by 4; this
process continues until the word count is reduced to O. When
the loading process is completed, register R contains a value
equal to the sum of the initial control image address plus the
in itial word count. Also, the final word count is 0, and bit po-
sitions 15-20 of register Ru 1 contain a value equal to the sum
of the initial contents plus 4 times the initial word count.
LOADING THE MEMORY WRITE PROTECTION LOCKS
The following diagrams represent the configuration of MMC,
register R, and register Ru 1 that are required to load the
memory write protection locks:
The instruction format is:
The contents of register Rare:
The contents of register Ru 1 are:
MEMORY LOCK CONTROL IMAGE
The initial address value in register R is the virtual address
of the first word of the memory lock control image, and word
length of the image is specified by the initial count in reg-
ister Ru1. A word count of 16 is sufficient to load the en-
tire block of memory locks. The memory lock registers are
treated as a circular set, with the register for memory ad-
dresses 0 through X 11 FF' immediately following the register
for memory addresses X 11 FEOOI through X 11 FFFF I; thus, a
word count greater than 16 causes the first registers loaded
to be overwritten.
Each word of the lock image is assumed
to be in the following format:
MEMORY LOCK LOADING PROCESS
Bit positions 15-20 of register Ru1 initially point to the first
512-word page of actual core memory addresses that is to
be controlled by the memory lock image. MMC moves the
lock image into the lock registers 1 word at a time, thus
loading the locks for 16 consecutive 512-word pages with
each image word.
As each word is loaded, the virtual ad-
dress of the lock image is incremented by 1, the word count
is decremented by 1, and the value in bit positions 15 -20
of register Ru1 is incremented by 4; this process continues
until the word count is "reduced to O. When the loading
process is completed, register R contains a va lue equal to
the sum of the initial lock image address plus the initial
word count. Also, the final word count is 0, and bit posi-
tions 15-20 of register Rul contain a value equal to the sum
of the initial contents plus 4 times the initial word count.
INTERRUPTION Of MMC
The execution of MMC can be interrupted after each word
of the control image has been moved into the specified con-
trol register. Immediatel
y
prior to the time that the instruc-
tion in the interrupt (or trap) location is executed, the
instruction address portion of the program status doubleword
contains the virtual address of the MMC instruction, register
R contains the virtual address of the next word of the control
image to be loaded, and register Ru1 contains a count of the
number of control image words remaining to be moved and a
value pointing to the next memory control register to be
loaded.
WAIT
WAIT
0/Vord index alignment, privileged)
WAIT causes the CPU to cease all operations until an inter-
rupt activation occurs, or unti
I
the computer operator man-
uall
y
moves the COMPUTE switch {on the processor control
panel or on the free-standing console} from the RUN posi-
tion to IDLE and then back to RUN.
The instruction ad-
dress porti on of the PSD is updated before the computer
begins waiting; therefore, while the CPU is waiting, the
INSTRUCTION ADDRESS indicators contain the virtual ad-
dress of the next location in ascending sequenceafterWAIT
and the contents of the next location are displayed in the
DISPLAY indicators {on the processor control panel and on
the free-standing console}.
If
any input/output operations
are bei ng performed when WAIT is executed, the operations
proceed to their normal termination.
When an interrupt activation occurs while the CPU is wait-
ing, the computer processes the interrupt-servicing routine.
Normally, the interrupt-servicing routine begins with an
XPSD instruction in the interrupt location, and ends with
an LPSD instruction at the end of the routi nee After the
LPSD instruction is executed, the next instruction to be
executed in the interrupted program is the next i nstructi on
in sequence after the WAIT instruction.
If
the interrupt is
to a single-instruction interrupt location, the instruction
in the interrupt location is executed and then instruction
execution proceeds with the next instruction in sequence
after the WAIT instruction. When the COMPUTE switch
is moved from RUN to IDLE and back to RUN while the
CPU is waiting, instruction execution proceeds with the
next instruction in sequence after the WAIT instruction.
If
WAIT is indirectly addressed and the indirect reference
address is nonexistent, the nonallowed operation trap {loca-
tion X1401} is activated.
The effective virtual address of
the WAIT instruction, however, is not used as a memory
reference (thus does not affect the normal operation of the
i nstructi on).
Control Instructions
79
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