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There are certain circumstances under which two of the
above nonal/owed operations can occur simultaneously.
The following operation codes (including their counter-
parts) are considered to be both nonexistent and privi-
leged: XIOC, XIOD I , X I 2C, and XI2DI. If any one of
these operation codes is used as an instruction while
the computer is in the slave mode, CC 1 and CC3 are
both set to lis; if bit 9 of XPSD is a
1,
the instruction
address portion of the new program status doubl eword is
incremented by 10.
If an attempt is made to access or
write into a memory region that is both nonexistent and
prohibited to the program by means of the memory con-
trol feature, CC2 and CC4 are both set to lis; if bit 9
of XPSD is a 1, the instruction address of the new pro-
gram status doubleword is incremented by 5.
2.
C::III instructions - the following additional functions
are performed when XPSD is being executed as a resu It
of a trap to location X ' 48
1
,
X
1
49
1
,
XI4AI, or XI4BI:
a:
The R field of the call instruction causing the
trap is logically inclusively ORed into bit posi-
tions 0-3 (CC) of the new PSD.
b.
If bit position 9 of XPSD contains a 1, the R field
of the call instructi-:>n causing the trap is added
to the instruction address portion of the new PSD.
If bit position 9 of XPSD contains a 0, the instruction ad-
dress portion of the new PSD always remains at the value
establ ished by the second effective doubleword.
Bit posi-
tion 9 of XPSD is effective only if the instruction is being
executed as the resul t of a nonall owed operati on trap or a
call instruction trap.
Bit position 9 of XPSD must be coded
with a 0 in all other cases; otherwise, the resul ts of the
XPSD instruction are undefined.
Affected: (EDL), (PSD)
If (I) 1 0
=
1, effect i ve address is vi rtua I
If (1)10
=
0, effective address is actual
PSD-EDL
ED2 0 _ 3 -
CC; ED25_7 -
FS, FZ, FN
ED28 -
MS; ED29 -
MM
ED2 10 - - DM; ED211 - - AM
ED2 15 _ 31 -
IA; ED2
34 _ 35 -
WK
ED2 37 _ 39 u CI, II, EI - C I , II, EI
If (1)8
=
1, ED2 55 _
59
-
RP
If (1)8
=
0, RP not affected
If nonexistent instruction, 1 -
CC1 then, if (1)9
=
1,
IA
+
8 - I A
If nonexi stent memory address, 1 -
CC2 then, if (1)9
=
1,
IA
+
4 - I A
If privileged instruction violation, 1 - CC3 then,
if
(1)9
=
1,
IA
+ 2 -
IA
If memory protection violation, 1 - - CC4 then, if (1)9
=
1,
IA +
1 - -
IA
If call instruction, CC u CALLS-11 - - CC then,
if (1)9
=
1, fA
+
C ALL 8- 11 - - fA
If (1)9
=
0, fA not affected
LRP
LOAD REGISTER POINTER
(Word index al ignment, privi leged)
LOAD REGISTER POINTER loads bits 23 through 27 of the
effective word into the register pointer (RP) portion of the
current program status doubleword.
Bit positions 0 through
22 and 28 through 31 of the effective word are ignored, and
no other portion of the program status doubleword is affected.
If the register pointer is loaded with a value that points to a
nonexistent block of general reg isters, the computer subse-
quentl y generates either all 1's or all OIS as the contents of
the nonexistent block of general registers, whenever an in-
struction designates a general register by means of the R field
or the reference address field.
Affected: RP
EW23-27-RP
MMC
MOVE TO MEMORY CONTROL
0Nord index al ignment, privi leged, continue
. after interrupt)
MOVE TO MEMORY CONTROL loads a string of one or
more words into one of the three blocks of memory control
registers (memory control registers are described under
"Memory Address Control" in Chapter 2). Bitpositions 12-14
of MMC are not used as an index register address; instead,
they are used to specify which block of memory control reg-
isters is to be loaded, as follows:
Bit positi on
12
13
14
1 0 0
o
1
0
0 0 1
Function
Load memory map block addresses
Load access protection
Load memory write protection locks
If bit positions 12-14 of MMC contain either a" OIS or more
than a single 1, the instruction produces an undefined result.
Also, if an attempt is made to load unimplemented memory
control storage, the contents of the general regi sters speci-
fied by the MMC instruction are undefined at the completion
of the instruction, and the implemented memory control stor-
age
(if
any) is not affected.
Bit positions 15-31 (reference address field) of MMC are ig-
nored insofar as the operation of the instruction is concerned,
and the results of the instruction are the same whether or not
MMC is indirectly addressed.
The R field of MMC designates
an
even-odd pair of general
registers (R and Ru 1) that are used to control the I oadi ng of
Control Instructions
77
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