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Code
Function
110
Enable ali levels selected by a 1 and disable all
levels selected by a O.
111
Trigger all levels selected by a 1. All such levels
that are currently armed advance to the waiting state.
INPUT jOUTPUT INSTRUCTIONS
II
Standard" SIGMA 6 I/O refers to the normal I/O system
consisting of input/output processors, device controllers,
and devices. This system handles normal communications
with standard peripherals such as printers, disks, tapes,
and so forth. When dealing with standard I/O operations,
the CPU uses the following five instructions:
Instruction Name
Start Input/Output
Halt Input/Output
T est Input/Output
Test Device
Acknowledge Input/Output Interrupt
Mnemonic
SIO
HIO
TIO
TOY
AIO
If execution of any input/output instruction is attempted while
the computer is in the slave mode (i. e. , whi Ie bit a of the
current program status doubleword is a 1), the computer un-
condi tiona II y aborts execution of the instruction (at the time
of operation code decoding) and traps to location X '40'.
110 ADDRESSES
The device to be operated on by an I/O instruction is selected
by the effective virtual address of the I/O instruction itself.
Indirect addressing and/or indexing are performed, as for
other word-addressing instructions, to compute the effective
virtual address of the I/O instruction. However, the effec-
ti ve address is not used as a memory reference (i. e., not
subject to memory mapping). For the SIO, HIO, TIO, and
TDY instructions, the 11 low-order bits of the effective vir-
tualaddress constitute an I/O address. FortheAIOinstruc-
tion, the device causing the interrupt returns its 11-bit I/O
address as part of the response to the AIO instruction.
An I/O address occupies bit positions 21 through 31 of the
effective virtual address, with bits 21, 22, and230ftheI/0
address specifying one of eight possible lOPs that can be con-
trolled by a CPU. The remainder of the I/O address is factored
into one of two forms, depending on bit 24, as follows:
Case I: Single-unit device controllers (bit 24 is 0)
Bits 25 through 31 of the I/O address (DC/Device) consti-
tute a single code specifying a particular combination of
devi ce controller and device.
Normally these codes refer
to devi ce controllers that drive only a single device, such
as card readers, card punches, line pri nters, etc.
Case II: Multiunit device controllers (bit 24 is 1)
82
Input/Output Instructi ons
Bit positions 25 through 31 of the I/O address contain a
3-bit device controller code (DC) in bit positions 25-27
and a 4-bit device code (Device) in bit positions 28-31.
This form of I/O address is used for device controllers (such
as magnetic tape and rapid access data file controllers) that
control information exchange with only one device at a time
(out of a set of as many as 16 devices).
110 UNIT ADDRESS ASSIGNMENT
Device controller numbers are normally assigned to a multi-
plexor lOP in numerical sequence, beginning with zero and
continuing through the highest number recognized by the lOP
(i. e., X,]', X'fi, X'17', or X'lF'). In the case of multiunit
device controllers, the device controller number must be in the
range
X
'0' through X '7' because the I/O address field structure
allows fora 3-bit multiunitdevice controller number. In the
case of si ngle-unit device controllers, any of the avai lable
numbers in the range X'O' through X'lF' may be assigned to
the device controller, providi ng that the Same number has not
already been assigned to a multiunit device controller. For
example, if device controller number X
'0'
is assigned to a
magnetic tape unit controller, the number X'O' cannot also
be used for a card reader (although the coding of the I/O
address field would be different in bit position 24). The I/O
address codes used by standard XDS software are
I/O address
Peripheral device designation
x'oao'
. lOP 0, devi ce controller 0, magnetic tape
unit 0
X'Oal'
lOP 0, device controller 0, magnetic tape
unit 1
X'Oa7'
lOP 0, device controller 0, magnetic tape
unit 7
X'OOl'
lOP 0, device controll er 1, keyboard/printer
X'002'
lOP 0, device controller 2, line pri nter
X'003'
lOP 0, device controller 3, card reader
X'004'
lOP 0, device controll er 4, card punch
X'005'
lOP 0, device controller 5, paper tape
reader/punch
110 STATUS RESPONSE
All I/O instructions result in the setting of condition code
CC1 and CC2 to denote the nature of the I/o response.
The R field of the I/O instruction specifies one of the gen-
eral registers that is to accept additional I/O response in-
formation during the execution of an I/O instruction. In
some situations, the programmer may want two sets of re-
sponse information loaded into the general registers, while
in other situations he may want only one set, or even no
information loaded into a general register. This control is
achieved by coding the R field of the I/O instruction. One
set of response information is loaded into register R and an-
other set may be loaded into register Rul. If the R field is
an even, nonzero number, registers Rand R
+
1 are each
loaded with response information. If the R field specifies
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