Xerox Sigma 6 Reference Manual page 50

an odd value, the product is loaded into the same register.
Overflow cannot occur.
Affected: (Rul), (C3, CC4
(R)16-31 x EH - - Rul
Condition code settings:
2 3 4 ResultinRul
a a
zero
a
1 negative
a
positive
Example 1, even R field value:
Before execution
EH X'FFFF '
(R) X 'xxxxOOOA
I
(R
u
1 )
xxxxxxxx
CC xxxx
Example 2, odd R field value:
EH
(R)
CC
X'FFFF '
X
I
xxxxOOOA
I
xxxx
MW MULTIPLY WORD
(Word index al ignment)
After execution
X'FFFF '
X
I
xxxxOOOA
I
X ' FFFFFFF6
1
xx01
X'FFFF '
X ' FFFFFFF6
1
xx01
MUL TIPL Y WORD multipl ies the contents of register Ru 1 by
the effective word, loads the 32 high-order bits of the prod-
uct into register R and then loads the 32 low-order bits of
the product into register Rul (overflow cannot occur).
If R
is an odd value, the result in register
R
is the 32 low-
order bits of the product. Thus, in order to generate a 64-
bit product, the R field of the instruction must be even and
the multiplicand must be in register R+1. The condition
code settings are based on the 64-bit product formed during
instruction execution, rather than on the final contents of
register R.
Affected: (R),(Rul),CC
(Ru
1)
x
EW
- - - +
R,
Ru 1
Condition code settings:
2 3 4 64-bit product
a
a
0 zero
a
negative
a
positive
result is correct, as represented in reg-
ister Ru 1
result is not correctly representable in
register Rul alone
42 Fixed-Point Arithmetic Instructions
OH
DIVIDE HALFWORD
(Halfword index alignment)
DIVIDE HALFWORD divides the contents of register R (treated
as a 32-bit fixed-point integer) by the effective hal fword
and loads the quotient into register R.
If
the absolute value
of the quotient cannot be correctly represented in 32 bits,
fixed-point overflow occurs; in which case CC2 is set to 1
and the contents of register R, and CC1, CC3, and CC4
are unchanged.
Affected: (R), CC2, CC3,
CC4
Trap: Fixed-point overflow
(R)~
E H - R
Condition code settings:
2 3 4
Result in R
a a a
zero quotient, no overflow
0
a
1
negative quotient, no overflow
a
1
a
positive quotient, no overflow
fixed-point overflow
If
CC2 is set to
1
and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X ' 43
1
with the
contents of register R, CC1, CC3, and CC4 unchanged.
ow
DIVIDE WORD
(Word index al ignment)
DIVIDE WORD divides the contents of registers Rand Ru 1
(treated as a 64-bit fixed-point integer) by the effective
word, loads the integer remainder into register R and then
loads the integer quotient into register Ru 1.
If
a nonzero
reml..li nder occurs, the remai nder has the same sign as the
dividend (original contents of register
R). If R
is an odd
value, DW forms a 64-bit register operand by extending
the sign of the contents of register R 32 bit positions to the
left, then divides the 64-bit register operand by the effec-
tive word, and loads the quotient into register R. In this
case, the remainder is lost and only the contents of register
R are affected.
If the absolute value of the quotient cannot be correctly
represented in 32 bits, fixed-point overflow occurs; in
which case, CC2 is set to 1 and the contents of register R,
register Rul, CC1, CC3, and CC4 remain unchanged; other-
wise, CC2 is reset to 0, CC3 and CC4 reflect the quotient
in register Ru1, and CCl is unchanged.
Affected: (R), (Rul), CC2 Trap: Fixed-point overflow
CC3, CC4
(R, Rul) -;- E W - R (remainder), Ru1 (quotient)
Condition code settings:
2 3 4
o a a
o a
Resul tin Ru1
zero quotient, no overflow
negative quotient, no overflow