Table of Contents
Advertisement
Table 9.
Program Status Doubleword Display
PSD Bit
PSD
Indicator
Function
Posiiton
Des ignat ion
PSW2
WRITE KEY
Write key
34-35
WK
INTRPT INHIBIT
Interrupt i nhi bits
37-39
CI, II, EI
CTR
Counter interrupt group inhibit
37
CI
I/O
Input/output interrupt group inhibit
38
II
EXT
External interrupts inhibit
39
EI
POINTER
Register block pointer
55-59
RP
PSW1
CONDITION CODE
Condition code
0-3
CC
FLOAT MODE
Floating-point mode controls
5-7
FS, FZ, FN
SIG
Significance trap mask
5
FS
ZERO
Zero trap mask
6
FZ
NRMZ
Norma
I
i ze mask
7
FN
MODE
Machine state/memory map controls
8-9
MS,MM
SLAVE
Master/slave mode control
8
MS
MAP
Memory map control
9
MM
TRAP
Arithmetic trap masks
10, 11
DM, AM
DEC
Decimal arithmetic fault trap mask
10
DM
ARITH
Fixed-point arithmetic overflow trap mask
11
AM
INSTRUCTION I.DDRESS
Address of next instruction to be executed
15-31
IA
PSWl or PSW2 position, the corresponding indicators in the
program status doubleword are altered (or unchanged, ac-
cording to current state of the 32 DATA switches below the
DISPLAY indicators).
INSTR ADDR
The INSTR ADDR (instruction address) switch is inactive in
the center position; the upper position (HOLD) is latching
and the lower position (INCREMENT) is momentary.
When
the switch is placed in the HOLD position, the normal pro-
cess of incrementing the instruction address portion of the
program status doubleword with each instruction execution
in inhibited. If the COMPUTE switch is placed in the RUN
position while the INSTRADDR switch is at HOLD, the in-
struction in the location pointed to by the value of the IN-
STRUCTION ADDRESS indicators is executed, repeatedly,
with the INSTRUCTION ADDRESS indicators remaining un-
changed.
If the COMPUTE switch is moved to the STEP
position while the INSTR ADDR switch is at HOLD, the in-
struction is executed once each time the COMPUTE switch
is moved to STEP; the INSTRUCTION ADDRESS indicators
remain unchanged unless the instruction is LPSD, XPSD, or
a branch instruction with the branch condition satisfied.
The foil owing operations are performed each time the
INSTR ADDR switch is moved from the center position to
the INCREMENT position:
1.
The current value of the INSTRUCTION ADDRESS
indicators is incremented by 1.
2.
Using the new value of the INSTRUCTION ADDRESS
indicators, the contents of the location pointed to by
the INSTRUCTION ADDRESS is displayed in the DIS-
PLAY i nd i cators.
ADDR STOP
The ADDR STOP (address stop) switch is used (with the
COMPUTE switch in the RUN position) to cause the central
processor to establ ish a halt condition and turn on the WAIT
indicator whenever the CPU accesses the memory location
whose address is equal to the SELECT ADDRESS value.
When the halt condition occurs, the instruction in the lo-
cation pointed to by the INSTRUCTION ADDRESS indicators
appears in the DISPLAY indicators.
The displayed instruc- .
tion is the one that would have been executed next, had
the halt condition not occurred.
If the halt condition is
caused by an instruction access, the value of the IN-
STRUCTION ADDRESS indicators (at the time of the halt)
is equal to the SELECT ADDRESS value.
If the halt condi-
tion is caused by execution of an instruction with an in-
direct reference address equal to the SELECT ADDRESS
value
(i
.e., by a direct address fetch), is caused by an in-
struction operand fetch, or is caused by an unsatisfi ed
conditional branch instruction whose effective address is
equal to the SELECT ADDRESS value, the value of the
INSTRUCTION ADDRESS indicators (at the time of the
halt) is 1 greater than the address of the instruction that
referenced the SELECT ADDRESS value.
Processor Control Pane I
95
Advertisement
Table of Contents
