Xerox Sigma 6 Reference Manual page 44

functions of the floating-point mode control bits are de-
scribed in the section "Floating-point Instructions".
Affected: CC, FS, FZ, FN
If
(1)10
=
I, EB
O
_
3
- - CC
If
(1)10
=
0, CC not affected
If (1)11
=
I, EB
5
_
7
- FS, FZ, FN
If
(1)11
=
0, FS, FZ, FN not affected
Condition code setti ngs, if (1)10
=
1:
2 3
4
{EB)2
XW EXCHANGE WORD
(Word index alignment)
EXCHANGE WORD exchanges the contents of register R
with the contents of the effective word location.
Affected: (R),(EWl),CC3,CC4
(R) -
(EWl)
Condition code settings:
2 3 4 Result in R
0 0 zero
0 1 negative
1 0 positive
ST8
STORE BYTE
(Byte index alignment)
STORE BYTE stores the contents of bit positions 24-31 of
register R into the effective byte location.
Affected: (EBl)
(R)24-31 - EBl
STH
STORE HAlFWORD
(Halfword index alignment)
STORE HAlFWORD stores the contents of bit positions 16-31
of register R into the effective halfword location.
If
the in-
formation in register R exceeds halfword data limits, CC2 is
set to 1; otherwise, CC2 is reset to O.
Affected: (EHl),CC2
(R)16-31 - EHl
Condition code settings:
2 3 4 Information in R
o
(R) 0 _ 16 ~ a
II
0' s or all 1 I s
(R)0-16
:I
all O's or all l's
36 load/Store Instructions
STW
STORE WORD
(Word index alignment)
STORE WOR D stores the contents of register R into the ef-
fective word location.
Affected: (EWl)
(R) - EWl
STD
STORE DOUBlEWORD
(Doubleword index alignment)
STORE DOU BlEWORD stores the contents of register R into the
32 high-order bit positions of the effectivedoubleword loca-
tion and then stores the contents of register Ru 1 into the 32 low-
order bit positions of the effective doubleword location.
Affected: (EDl)
(R) - EDl
O
_
31
; (Ru1) - EDl
32
_
63
Example I, even R field value:
(R)
(Ru
I)
(EDl)
=
Before execution
X ' 01234567'
X ' 89ABCDEF'
xxxxxxxxxxxxxxxx
Example 2, odd R field value:
(R) X ' 89ABCDEF'
(EDl)
=
xxxxxxxxxxxxxxxx
After execution
X '01234567
1
X'89ABCDEF'
X ' 0123456789ABCDEF'
X'89ABCDEF'
X '89ABC DEF89ABC DEF'
STS
STORE SELECTIVE
0/Vord index alignment)
Register Ru1 contains a 32-bit mask. If R is an even value,
STORE SELECTIVE stores the contents of register R into the
effective word location in those bit positions sel·ected by a I
in corresponding bit positions of register Ru 1; the effective
word remains unchanged in those bit positions selected by a
o
in corresponding bit positions of register Rul.
IfR isan odd value, STS logically inclusiveORs the contents
of register R with the effective word and stores the result
into the effective word location. The contents of register
R are not affected.
Affected: (EWl)
If
R is even, [(R)n(Ru
1)]
u
[EWn(~)]
- EWl
If
R is odd, (R) u EW - EWl
Example 1, even R field value:
(R)
(Ru 1)
EW
Before execution
XI 12345678
1
XI FOFOFOFO'
xxxxxxxx
After execution
XI 12345678'
XI FOFOFOFO '
X'1x3x5x7x '