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level accepts interrupt signals from the standard
I/o
system. The
I/o
interrupt location is assumed to contain
an EXCHANGE PROGRAM STATUS DOUBLEWORD (XPSD)
instruction that transfers program control to a routine for
servicing all I/O interrupts. The I/O routine then contains
an ACKNOWLEDGE I/o INTERRUPT (AIO) instruction that
identifies the source and reason for the interrupt.
The control panel interrupt level is connected to the INTER-
RUPT buttons on the processor control panel. The control
panel interrupt level can thus be triggered by the computer
operator, allowing him to initiate a specific routine.
The interrupts in the input/output group can be inhibited or
permitted by means of bit position 38 (II) of the program
status doubleword. If II is a 0, the interrupts in the I/O
group are allowed to interrupt the program being executed.
However, if the II bit is a 1, the interrupts are inhibited
from interrupting the program.
POWER FAIL-SAFE FEATURE
The two power fail-safe interrupt levels, which cannot be
disabled, disarmed, or inhibited, are used to enter routines
that save and restore volatile information (e. g., registers,
interrupt environment, etc.) in case of primary powerfailure.
When primary voltage drops below safe limits, the power off
interrupt is triggered. Typically, a power off routine stores
volati Ie information in main memory to faci litate recovery,
halts all I/O operations, and ends in a waiting state. When
primary power returns to safe limits, the power on interrupt
is triggered. Typically, a power on routine restores infor-
mation from main memory and prepares to resume processing.
(Note: When power is restored, software timeouts for I/O
operations may occur.) Because the power on interrupt has
a hi gher priority than the power off interrupt (see Table 2),
a power failure cannot interrupt a power on routine before
the system is restored to a predi ctab Ie state (registers
restored, etc.). Since main frame power supplies maintain
voltages for five milliseconds after detecting an imminent
power failure, the total time of the power on and power off
routines must be less than five mi Iliseconds.
EXTERNAL INTERRUPTS
A SIGMA
6
system can contain up
fl.'
14 groups of optional
interrupt levels, with 161evels in each group. As shown in
Figure 6, the groups can be connected in any priority sequence.
All external interrupts can
be
inhibited or permitted by means
of bit position 39 (EI) of the program status doubleword. If
EI is a 0, external interrupts are allowed to interrupt the
program; however, if EI is a 1, all external interrupts are
inhibited from interrupting the program.
STATES OF AN INTERRUPT LEVEL
A SIGMA 6 interrupt level is mechanized by means of three
flip-flops.
Two of the flip-flops are used to define any of
four mutually exclusive states: disarmed, armed, waiting,
and active. The third flip-flop is used as a level-enable.
The various states and the conditionscausing them to change
state (see Figure 7) are described in the following paragraphs.
DISARMED
When an interrupt level is in the disarmed state, no signal
to that interrupt level is admitted; that is, no record is re-
tained of the existence of the signal, nor is any program
interrupt caused by it at any time.
ARMED
When an interrupt level is in the armed state,
it
can accept
and remember an interrupt signal. The receipt of such a sig-
nal advances the interrupt level to the waiting state.
WAITING
When an interrupt level in the armed state receives an in-
terrupt signal, it advances to the waiting state, and remains
External
Input
Active, waiting, or
r----------------------
:
~
I
d;sarmed stale
I
O;sabled stale
Trigger
Input
1 - .
- - - - 0
~:
Remember
Armed state
:
interr~pt
Enabled state
I
I
---------------------~
Group n
inhibit
=
1
on
off
Group n
inhibit
=
0
WAITING STATE
---------------------------------------------
I
Note: The armed, disarmed, waiting, and active states are controlled by two flip-flops and the enabled/disabled
I
states are controlled by
the level-enable flip-flop.
Figure 7.
Operational States of an Interrupt Level
20
Interrupt System
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