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the instruction execution cycle. If a trap does occur
during the instruction execution, the condition code
is normally reset to the value it contained before the
instruction was started, and then the appropriate trap
location is activated.
13. Actions taken by the computer for those trap con-
ditions that may be invoked by the execution of
the instruction are described.
The description
includes the criteria for the trap condition, any
controlling trap mask or inhibit bits, and the action
taken by the computer.
In order to avoid unnecessary
repetition, the two trap conditions that apply to all
instructions (i. e., nonallowed operations and
watchdog timer runout) are not described for each
instruction.
14. Some instruction descriptions provide one or more
examples to illustrate the results of the instruction.
These examples are intended onl y to show how the
instructions operate, and not to demonstrate their
full capability. Within the examples, hexadecimal
notation is used to represent the contents of general
registers and storage locations {condition code set-
tings are shown in binary notation. The character
"x"
is used to indicate irrelevant or ignored information.
Table 4.
Glossary of Symbolic Terms
Term
( )
AM
R
Ru
1
x
RA
EVA
Meaning
Contents of.
Fixed-point arithmetic trap mask - bit 11 of
the program status doubleword.
If
this bit is
a 1, the computer traps to location X ' 43 1 after
executing an instruction that causes fixed-
point overflow; if this bit is a 0, the computer
does not trap to location X'43 1 •
Instruction register - the internal CPU register
used to hold instructions obtained from memory
whi Ie they are being decoded.
General register address value - the 4-bit con-
tents of bit positions 8-11 (the R field) of an in-
struction word, also expressed symbolically as
(1)8-11' In the instruction descriptions, reg-
ister R is the general register (of the current
register block) that corresponds to the R field
add ress va I ue •
Odd register address value - register Ru 1 is the
general register pointed to by the value obtained
by logically ORing 0001 into the address value
for register R. Thus, if the R field of an instruc-
tion contains an even value, Ru 1
=
R
+
1, and if
the R field contains an odd value, Ru 1
=
R.
Index register address value - the 3-bit contents
of bit positions 12-14 (the X field) of an instruc-
tion word. If X
=
°
for an instruction, no index-
ing is performed. If X
t-
a
for an instruction, in-
dexing is performed (after indirect addressing if
indirect addressing is called for) with general
register X in the current register block.
Reference address - the contents of bit positions
15-31 of an instruction word. This 17-bit field
is capable of directly addressing any general
register in the current register block (by using
a value in the range 0-15) or any word in core
memory in the address range 16 through 131,07l.
This address value is the initial address value for
any subsequent address computations, memory
mapping, or both computation and mapping.
Effective vIrtual address - the virtual address
value obtained as a result of indirect addressing
and/or indexing.
This address value is
30
Instruction Repertoire
Term
EBL
EB
EHL
EH
EWL
EW
EDL
ED
CC
FN
Meaning
independent of the program1s actual location
in core memory, and is the final address value
before memory mapping is performed.
Effective byte location - the byte location
pointed to by the effective virtual address of
an instruction for a byte operation.
Effective byte - the 8-bit contents of the
effective byte location, or (EBL).
Effective halfword location - the halfword lo-
cation pointed to by the effective virtual ad-
dressof an instruction fora halfword operation.
Effective halfword - the 16-bit contents of
the effective halfword location, or (EHL).
Effective word location - the word location
pointed to by the effective virtual address of
an instruction for a word operation.
Effective word - the 32-bit contents of the
effective word location, or (EWL).
Effective doubleword location - the double-
word location pointed to by the effective
virtual address of an instruction for a double-
word operation. If an odd-numbered word lo-
cation is specified for a doubleword operation,
the low-order bit of the effective address field
(bit position 31) is automatically forced to 0.
Thus, an odd-numbered word address (referring
to the middle of a doubleword) designates the
same doubleword as an even-numbered word
address, when used for a doubleword operation.
Effective doubleword - the 64-bit contents of
the effective doubleword location, or (EDL).
Condition code - a 4-bit value (whose bit
positions are labeled CC 1, CC2, CC3, and
CC4) that is establ ished as part of the exe-
cution of most SIGMA 6 instructions.
Floating normal ize mode control - bit 7 of the
program status doubleword.
If this bit is a 0,
the results of floating-point additions and
subtractions are to be normalized; if this bit
is a 1, the results Clre not normalized.
I
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