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WRITE DIRECT INTERNAL COMPUTER CONTROL (MODE 0)
In this mode, the condition code is unconditionally set
accordi ng to the states of the four SE NSE switches on the
processor control panel.
If
a particular SENSE switch is
set, the corresponding bit of the condition code is set to 1;
if a SENSE switch is reset, the corresponding bit of the
condition code is reset to 0 (see "SENSE" in Chapter 5).
SET INTERRUPT INHIBITS
The following configuration of WD can be used to set the
interrupt inhibits (bit positions 37-39 of the PSD).
A logical inclusive OR is performed between bits 29-31 of
the effective virtual address and bits 37-39 of the PSD.
If
any (or all) of bits 29-31 of the effective virtual address are
l's, the corresponding inhibit bits in the PSD are set to l's;
the current state of an inhibit bit is not affected
if
the cor-
responding bit position of the effective virtual address con-
tains a O.
RESET INTERRUPT INHIBITS
The following configuration .)f WD can be used to reset the
interrupt inhibits:
If
any (or all) of bits 29-31 of the effective virtual address
are l's the corresponding inhibit bits in the PSD are reset to
O's; the current state of an inhibit bit is not affected if a
corresponding bit position of the effective virtual address
contains a O.
SET ALARM INDICATOR
The following configuration of WD is used to set the ALARM
indicator on the maintenance section of the processor con-
trol panel:
If
the COMPUTE switchontheprocessorcontrol panel isinthe
RUN position and the AUDIO switch on the maintenance sec-
tion of the processor control panel is in the ON position, a
WOO-Hz signal is transmi tted to the computer speaker. The
signal may be interrupted by moving the COMPUTE switch
to the IDLE position, by moving the AUDIO switch to the
OFF position, or by resetting the ALARM indicator.
RESET ALARM INDICATOR
The following configuration of WD is used to reset the
ALARM indicator:
The ALARM indicator is.also reset by means of either the CPU
RESET/CLEAR switch or the SYS RESET/CLEAR switch on the
processor control panel.
TOGGLE PROGRAM-CONTROLLED-FREQUE NCY
FLIP-FLOP
The following configuration of WD is used to "toggle" the
CPU program-controlled-frequency (PCF) flip-flop:
The output of the PCF flip-flop is transmitted to the computer
speaker through the AUDIO switch on the maintenance secti on
of the processor control pane I. If the PCF
fI
i p-fl op is reset whe n
the above configuration of WD is executed, the WD instruction
sets the PCF fI ip-floPi if the PCF fI ip-flop was previ ously set,
the WD instruction resets it. A program can thus generate a
desired frequency by toggling (setting and resetting) the PCF
fl ip-flop at the appropriate rate.
Execution of the above
configuration of WD also resets the ALARM indicator.
WRITE DIRECT, INTERRUPT CONTROL (MODE 1)
The following configuration of WD is used to set and reset
the various states of the individual interrupt levels within
the CPU interrupt system:
Bits 28 through 31 of the effective address specify the iden-
tification number (see Table 2) of the group of interrupt
levels to .be controlled by the WD instruction.
The R field of the WD instruction specifies ageneral register
that contains the selection bits for the individual interrupt
levels, excluding Power on/Power off, within the specified
group (see Table2). Bit position 160f register R contains the
selection bit for the highest-priority (lowest-numbered) in-
terrupt level within the group, and bit position 31 of register R
contains the selection bit for the lowest-priority (h ighest-
numbered) interrupt level within the group. Each interrupt
level in the designated group is operated on according to the
function code specifiedbybits21 through 23 of the effective
address of WD. The codes and their associated functions are as
follows:
Code
Function
000
Undefi ned
OOlt
Disarm all levels selected by a 1; all levels selected
by a 0 are not affected.
OlOt
Arm and enable all levels selected by a 1; all level s
selected by a 0 are not affected.
Ollt
Arm and disable al/ levels selected by a 1; all levels
selected by a 0 are not affected.
100
Enable all levels selected by a 1; all levels selected
by a 0 are not affected.
101
Disable all levels selected by a 1; all levels selected
by a 0 are not affected.
t These codes c I ear the current interrupt, i. e.
I
remove from
the active or waiting state all levels selected by a 1 (see
Figure 7).
Control Instructions
81
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