Status Information For Sio - Xerox Sigma 6 Reference Manual

an odd-numbered general register, then only register R is
loaded with response information. However, if the R field
is 0, Rand Rul are not loaded with response information.
Also, if RI- 0 and CCl is set to 1 as a result of the opera-
tion, no status information is returned to Rand Rul. The
I/O response information loaded into the general register
for 510, HIO, TIO, and TDV instructions is in the following
format:
Word into register R
Word into regi ster Ru 1
Current Command Doubleword Address. After the addressed
devi ce has received an order, this field contai ns the 16
high-order bits of the core memory address for the command
doubleword (see "IOP Command Doublewords
ll
)
currently
being processed for the addressed device.
Status. The meaning of this field depends on the particular
I/O instruction being execu+-ed and upon the selected I/O
device (see Table 8).
Byte Count. After the addressed device has received an
order, this field contains a caunt of the number of bytes yet
to be transmitted to or from memory by the operation called
for by the order.
See the AIO instruction description for the format of I/O
response i nformati on for AIO.
510 START INPUT/OUTPUT
\:'Nord index alignment, privileged)
START INPUT/OUTPUT is used to initiate an input or out-
put operation with the device selected by the I/O address
(bits 21-31 of the effective vi rtua I address of the instruction).
510 utilizes data in general register
0,
which is assumed
to have the following content when 510 is executed.
General register 0 is temporarily dedicated during the exe-
cution of an 510 instruction to specify the starting double-
word address for the lOP command list. The doubleword
address in register 0 is the 16 high-order bits of a memory
address; thus, the address in register
0
always specifies an
even-numbered word location. (The lOP command list is
described in "10P Command Doublewords", Chapter 4.)
If I/O address recogniti.on exists in the I/O system, and the
device controller and device are in the "ready" condition
and no interrupt condition is pending, the 510 is accepted
and the device is started
0.
e., advanced to the "busy"
condition).
If
the 510 is accepted, the first command
doubleword address is loaded into the IOPcommand address
counter associated with the device controller specified by
the I/O address of the 510 instruction. Then, if the device
is in the "automatic" mode, it requests an order from the
lOP. The lOP loads the first command doubleword of the
1/
0 command list into its appropriate regi sters and transmits
the order to the device.
The CPU condition code provides an indication of whether
the I/O address specified by the 510 instruction was or was
nC;;t recognized by the I/O system and whether the 510 in-
struction was or was not accepted by the device (i. e., whether
the device did or did not advance to the "busy" condition).
The condition code settings for 510 are:
1
2 3 4
o
0
Resul t
I/O address recognized and 510 accepted
I/O address recognized but 510 not
accepted
o
o
lOP address recognized but device con-
troller either is attached to a "busy"
selector lOP that cannot return status at
this time or, for specific device con-
troll ers, is currentl y "busy" wi th another
devi ceo No status informati on is returned
to general registers.
I/O address not recognized and 510 not
accepted; no status i nformati on is returned
to general registers.
STATUS INFORMATION FOR SIO
In the event that the 510 instruction was not accepted
(i. e., CC 1
=
0
and CC2
=
1), the status information returned
as a part of the I/O response provides indications of Nhy
the 510 instruction was not accepted. If the 510 instruction
has been coded with an R field value of
0,
or if CCI (as a
result of the execution of this instruction) is a I, only the
condition code settings are available. If the R field value
is odd, register R contains the fol lowing information:
Bit
Position Function
o
Interrupt pendingj if this bit is 1, the addressed
device has requested an interrupt and the inter-
rupt has not been acknowledged by an AIO in-
struction. I/O interrupts can be achieved by coding
of the flag portion of the I/O command double-
word. I/O interrupts can also be achieved by using
M modifiers in the basic order to the device (M bits
in the Order portion of the command doubleword).
In either case, the device wil I not accept a new
SIO instruction until the interrupt-pending condi-
tion is
cleared
(i.e.,
the condition code settings
for the SIO instruction will indicate IISIO not
accepted
ll
if the interrupt-pending condition is
present in the addressed device.
Input/Output Instructions 83