Xerox Sigma 6 Reference Manual page 79

register 15), the first register to be loaded from the stack
is register R
-+
CC - 1, and the contents of the current top-
of-stack location become the contents of this register. The
last register to be loaded is register R.
If there is a sufficient number of words in the stack to load
all of the specified registers, PLM operates as follows:
1.
Registers R + CC -1 to register R are loaded in a de-
scending sequence, beginning with the contents of
the location pointed to by the current top-of-stack
address (SPD15-31) and ending with the contents of
the location pointed to by the current top-of-stack
address minus CC-1.
2. The current top-of-stack address is decremented by
the value of CC, to point to the new top-of-stack
location.
3. The space count (SPD33-47) is incremented by the
value of CC and the word count is decremented by
the.value of CC.
4.
The condition code is set to reflect the new status
of the word count.
Affected: (SPD), (R+CC-1) Trap: Push-down stack limit
to
(R),
cc
((SPD)15_31) - R
+
CC -1, •.. ,
{(SPD)15_31
-lcc-1\
) - R
(SPD)15_31 - CC -SPD 15 _ 31
(SPD)33-47
+
CC -SPD 33 _ 47
(SPD)49_63 - CC --SPD 49-63
Condition code settings:
2 3 4
o
o
o
0
o
Result of PLM
word count
>
0
1
instruction completed
o
0
word count
=
0
o
0
o
word count
<
CC,
TW
=
1
o
0
word count
=
0,
TW
=
1
o
0
space count
=
0,
word
count
<ee,
TW
=
1
o
o
o o
o o
o
space count
=
0,
word
count
=
0, TW
=
1
15
space count + CC >2 -1,
TS
=
1
15
space count + CC >2
-1,
word count
<
CC, TS
=
1,
and TW
=
1
15
space count
+
CC >2 -1,
word count
=
0, TS
=
1,
and TW
=
1
instruction
aborted
If the instruction starts loading from an existent region of
memory and then crosses a memory page boundary into an
inaccessible memory region, either the memory protection
trap or the nonexistent' memory address trap can occur. In
either case, the trap is activated with the condition code
unchanged from the val ue it contai ned before the executi
on
of PLM. The effective address of the instruction permits
the trap routine to compute how many registers have been
loaded. Since it is permissible to use indexing or indirect
addressing through a general register, or even to execute
an instruction located in a general register, a trapped
PLM
instruction may have already overwritten the index, direct
address, or the PLM instruction itself, thus destroying any
possibility of continuing the program successfully.
If
such
programming must be done, it is advisable that the register
containing the direct address, index displacement, or in-
struction be the last register loaded by the PLM instruction.
If the address of the elements within the stack (pointed to
by the top-of-stack address) is in the range 0 through 15,
then the words to be loaded are taken from the general re-
gisters rather than from core memory. In this case the re-
sults will be unpredictable if any of the source registers
are also used as destination registers.
MSP MODIFY STACK POINTER
(Doubleword index alignment)
Reference address
MODIFY STACK POINTER modifies the stack pointerdouble-
word, located at the effecti ve doubl eword address of MS P,
by the contents of register R. Register R is assumed to have
the following format:
Bit positions 16 through 31 of register R are treated as a
signed integer, with negative integers in f"'NCls complement
form (i. e., a fixed-point halfword). The modifier is alge-
braicallyadded to the top-of-stack address, subtracted from
the space count, and added to the word count in the stack
pointer doubleword. If, as a result of MSP, either the space
count or the word count would be decreased below 0 or in-
creased above 2 15 _1, the instruction is aborted.
Then, the
computer either traps to location X ' 42
1 or sets the condition
code to refl ect the reason for aborti ng, dependi ng on the
stack limit trap inhibits.
If the modification of the stack pointer doubleword can be
successfully performed, MSP operates as follows:
1.
The modifier in register R is algebraically added to the
current top-of-stack address (SPD}J 5-31, to poi nt to a
new top-of-stack location.
(If
the modifier is negative,
it is extended to 17 bits byappending a high-order 1.)
2. The modifier is algebraically subtracted from the cur-
rent space count (SPD 33 - 47 ) and the result becomes
the new space count.
3. The modifier is algebraically added to the current word
count {SPD49-63} and the result becomes the new word
count.
4. The condition code is set to reflect the new status of
the new space count and new word count.
Affected: (SPD), CC Trap: Push-down stack limit
Push-Down Instructions 71