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CONDITION CODES FOR FLOATING-POINT INSTRUCTIONS
The condition code settings for floating-point instructions
are summarized in Table 7.
The following provisions apply
to all floating-point instructions:
1.
Underflow and overflow detection apply to the final
characteristic, not to any lIintermediate
ll
value.
2.
If a floating-point operation results in a trap, the
original contents of all general registers remain
unchanged.
3.
All shifting and truncation are performed on absolute
magnitudes.
If
the fraction is negative, then the two's
complement is formed after shifting or truncation.
FAS
FLOATING ADD SHORT
(Word index al ignment, optional)
The effective word and the contents of register R are loaded
into a set of internal registprs and a low-order hexadecimal
zero (guard digit) is appended to both fractions, extending
them to seven hexadecimal digits each.
FAS then forms the
floating-point sum of the two numbers.
If
no floating-point
arithmetic fault occurs, the sum is loaded into register R as
a short-format fl oati ng-poi nt number.
Affected: (R), CC
(R)
+
EW-R
Traps: Unimplemented in-
struction, floating-
point arithmetic fault
FAl
FLOATING ADD LONG
(Doubleword index al ignment, optional)
The effective doubleword and the contents of registers Rand
Ru1 are loaded into a set of internal registers.
The operation of FAL is identical to that of F LOA TIN G ADD
SHORT (FAS) except that the fractions to be added are each
14 hexadecimal digits long, guard digits are not appended
to the fractions, and R must be an even value for correct re-
sults. If no floating-point arithmetic fault occurs, the sum
is loaded into registers Rand Ru1 as a long-format floating-
point number.
Affected: (R), (Ru1), CC
(R, Ru1) +
ED -
R, Ru1
Traps: Unimplemented in-
struction, floating-
point arithmetic fault
FSS
FLOATING SUBTRACT SHORT
(Word index alignment, optional)
The effective word and the contents of register R are loaded
into a set of i nterna
I
registers.
FLOATING SUBTRACT SHORT forms the two's complement
of the effective word and then operates identicall y to
FLOATING ADD SHORT (FAS).
If no floating-point arith-
metic fault occurs, the difference is loaded into register R
as a short-format fl oati ng-poi nt number.
Affected: (R), CC
(R) - EW-R
; Traps: Unimplemented in-
struction, floating-
point arithmetic fault
Table 7. Condition Code Settings for Floating-Point Instructions
Condition Code
Mean i ng if no trap to location X'44
t
occurs
I
Meaning if trap to location X'44' occurs
1
2
3
4
0
0
0
0
A x 0,
O/A,
or
-A + A
CD with
FN=l
I
I
*(l)
0
0
0
1
N <0
norma
*
0
0
1
0
N > 0
results
*
0
1
0
0
*(l)
div ide by zero
I
0
1
0
1
*
overflow, N < 0
always trapped
0
1
1
0
*
overflow, N > 0
~I
:
0
0
0
-A
+
A
CD
-A + A
I
0
0
1
N
<
°
I
>
2
postnorma'-l
FS=O, FN=O,
and
N < 0
> 2 postnormal-
FS=l, FN=O, and no
0
1
0
N > 0
izing shifts
no underflow
N > 0
I
izing shifts
underflow with FZ= 1
1
1
0
0
underflow with FZ=O and no trap by FS=l
CD
*
1
1
0
1
*
underflow, N < 0
l
FZ=l
1
1
1
0
*
underflow, N >0
Notes:
CD
result ~et to true zero
- -
(l) 11*11
indicates impossible configurations
@
applies to add and subtract only where FN=O
Floating-Point Arithmetic Instructions
53
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