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The access control codes are assigned as follows:
I
AC
I
AC
I
AC
IHI
AC
I
AC
I
1
·Virtual addressts
X
I
600 ' - X
I
7FF
1
1
Vi rtua I addresses
XI4001-X I 5FF'
+
Vi r tua I
~ddresses
X'lFEOOI-XllFFFF'
(virtual page 255)
Virtual addresses
XI2001-X I 3FF'
Virtual addresses
XllFCOOI-XllFDFF'
Vi rtua I addresses
XllOI-XllFF'
(virtual page 0)
The memory page addresses and access control codes can
be changed only by the privileged instruction MOVE
TO MEMORY CONTROL (see "Control Instructions").
When the CPU is operating in the mapping mode, all mem-
ory references used by the program (including instruction ad-
dresses) whether direct, indirect, or indexed, are referred to
as virtual addresses.
Virtual addresses in the range 0 through
15 are not used to address core memorYi instead, the 4 low-
order bits of the virtual address comprise a general register
address.
However, if an instruction produces a virtual ad-
dress greater than 15, the 8
h~gh-order
bits of the virtual
address are used to obtain the appropriate memory page ad-
dress and access control codes.
For example, if the 8 high-
order bits of the virtual address are 0000 0000, the first page
address code and the first access control code are used; if
the 8 high-order bits of the virtual address are 0000 0001,
the second page address and access control codes are used;
and so on, through the 256th page address and control codes.
Thus, each 512-word page of virtual addresses is associated
wi th its own memory page address and access control codes.
When the memory map is accessed, the CPU performs a test
to determine whether or not there are any inhibitions on using
the virtual address by a slave program.
(If
the CPU is in the
master mode, this test is not performed.) The 2-bit access
control code is interpreted as follows:
AC Function
00
The slave program can write into, read from, or access
instructions from this page of virtual addresses.
01
The slave program cannot write into, but can read from
or access instructions from this page of virtual addresses.
10
The slave program cannot write into or access instruc-
tions from, but can read from this page of virtual ad-
dresses.
11
The slave program is denied any access to this page of
virtual addresses.
If the instruction being executed by the slave program fails
this test, the instruction execution is aborted and the com-
puter traps to location X 1 40 ' , the "nonallowed operation"
trap (see
II
Trap System").
If the instruction being executed by the slave program passes
this test (or the CPU is in the master mode), the page address
bits in the accessed byte of the memory map replace the 8
high-order bits of the virtual address, to produce the actua I
address of the core memory location to be used by the in-
struction.
If
the page address bits in the accessed byte of the memory
map are all O'S, and when combined with 9 low-order bits
of the virtual address, an actual address is produced that
corresponds to a word address in the range 0 throug h 15,
the corresponding general register in the current register
block is not accessed.
In this one particular instance, a
word address in the range 0 through 15 corresponds to actual
core memory locations rather than general registers.
Figure 5 illustrates the address modification and mapping
process for an indirectly addressed, indexed, halfword
operation. As the figure shows, word address 1 is the
contents of the reference address field in the instruction
stored in memory.
The instruction is brought into the in-
struction register, and word address 1 (assumed to be greater
than 15) is converted from a virtual address to an actuol ad-
dress by the memory map.
The 17 low-order bi ts of the core
memory location pointed to by word address I, labeled word
address 2, then replaces word address 1 in the instruction reg-
ister. The index register designated in the X field of the in-
struction is then aligned for incrementing at the halfword-
address level, the final virtual (effective) address is formed,
and the effective address (assumed to be greater than 15) is
also transformed, through the memory map.
The final 19-
bit core l1)emory address, which automatically contains a
low-order 0, is then used to access the halfword to be used
as an operand for the instruction.
MEMORY WRITE LOCKS
The access control bits in the memory map provide access
protection, through inhibitions imposed on slave programs.
However, this protection is only available when the memory
map is in effect, and is only operative with respect to slave
programs. A memory protection feature, independent of the
memory map, is provided by a lock and key technique. A
I
2-bit write-protect lock
(WL)
is provided for each 512-
word page of actual core memory addresses.
The write-
protect locks consist of 256 2-bit write locks, each as-
signed to a 512-word page of actual addresses as follows:
I
WL
I
WL
I
WL
I
WL
I
WL
I~ ~
WL
I
WL
I
I
1
•
+.
Actua I addresses
Actual addresses
X I 600 1 -X'7FF'
X'I FEOOI-XIIFFFF'
Actual addresses
(memory page 255)
XI4001-X I 5FF'
Actual addresses
XI2001-X I 3FF'
Actual addresses
0-XI1FF'
(memory page 0)
Actual addresses
XIIFCOOI-XIIFDFF'
The write-protect locks can be changed on Iy by the execu-
tion of the privileged instruction MOVE TO MEMORY CON-
TROL (see Control Instructions).
Memory Address Control
15
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