Table of Contents
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CENTRAL PROCESSOR UNIT
(CPU)
Standard Features:
•
Decimal arithmetic unit
•
Memory
mop
•
Access protection
•
Memory write protection
•
Two register blocks
•
Power fail-safe
•
Two reol-time clacks
•
External interface (direct
VOl
Optional Features:
•
Two additional real-time clacks
•
30
additional register blocks
•
Floating-point arithmetic
•
External priarity interrupt system
(up to
224 levels)
MEMl :: - --- - - - - r=-
--=-
~ :-eM-:1-
uNiT - -
-1
Standard Features:
I
Standard Features:
I
32,768 words
Two ports (multiocess)
Two-way interleaving
Four-way interleaving
Parity checking
Optional Features:
•
Four additional ports
•
Memory
system
expandable by
adding up to three additional
32K memory units
I
16,384 or
I
I
32,768 words
I
I
•
Two
ports
(multiaccess)
I
•
Two-way interleaving
I
•
Four-woy interleaving
I
I
•
Parity checking
I
I
Optional Features:
I
I
•
Four odditional ports
:
L--.---T'""""'-----'
:
I
:
I
' - -___ .== .
.::.:=.~.=.=.=.===
. . ==.= .
.:.r ..............•.....................•...•...•....••........•.•....••.•.•.
!
...-_ _ _ _ _ -..1. _ _ _ _ :..'_--. - - - - - - - - - - - - - - - - - - - .
MUlTIPLEXING INPUT/OUTPUT
r -
MIOP EXPANsION OPTION -
-,
r
l
- -smcroRi~puT/OUTPUT-1
PROCESSOR (MIOP)
(ONE PER MIOP)
I
PROCESSOR (SlOP)
I
Standard Features:
Standard Features:
I
Stondard Features:
I
•
One group of eight subchonnels
One group of eight subchannels
I
Single-byte interface
I
•
Single-byte interface
•
Single-byte interface
I
Four-byte interface
I
•
Four-byte interface
I
I
Optianal Features:
Two additional groups of eight
subchannels
Accommodates:
One device controller
per subchonnel
I
r;:--1--,
r.:-.J.._:j
I
SDIENVGICLEE UNIT
I
IMULTI~UNIT
I
I ···
DEVICE
I
~~~O'!:!:E.!J
IE£!'I~~L!RJ
I
I
_..l-:::-1
I
r-----,
[1/ 0
~V~ J
r
-t 1/0 DEVICE I
I '- ____
..J
I
L
fiiO
DEViCE
1
. , (Up to
I
~~e~~J
Optional Features:
I
Accommodates:
I
I
•
32 device control/en
I
Two additional groups aF eight
subchonnels
Accommodates:
•
One device contraller
per
subchannel
L __ , _____ , __
I
I
r.-
J
--:1
r.--1-~
I
SINGLE UNIT I
I MULTI-UNIT
I
I DEVICE
I . • '1 DEVICE
I
I
CONTROLLERJ
I CONTROLLER
I
I . . -
T - -
L..;.-T- .....
I
I
Ii/O~VlC~
.
~
rVODEvlcE]
L.. _ _ _ _ "
I
L~
_ _
I
.
L .-
Vo
DeVICE!
-I
(Up 10
:
Ll~de~ces)
J
L - - r - - - - - - - J
I
I
I
I
~------,
I
I
r-J.--, r-J--,
I
DEVICE
I
I DEVICE
I
ICONTROlLERI' • 'ICONTROLLERI
L_,---i
L _ , _ - J
I
I
r--L-,~_J-:1
~O ~~~
lYO
~~~
--------------Standard-$PMd peripheral devices - - - - - - - - - - - -.....
pl
1-
High-speed peripheral devices
-I
Note: Standard units and pracessan are shown enclosed with solid barder lines. Optional units, processors, device contrallen,
- - and devices are enclosed with clashed barder lines. Standard and optional features within a unit or processor are as listed.
Figure 1.
A Typical SIGMA 6 System
2
General Characteristics
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