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3.
Between instruction iterations: An interrupt is also
permitted to occur during the execution of the follow-
ing multiple-operand instructions:
Move Byte String (MBS)
Compare Byte String (CBS)
Translate Byte String (TBS)
Translate and Test Byte String (TTBS)
Edit Byte String (EBS)
Decimal Multiply (OM)
Decimal Divide (00)
Move tt::) Memory Control (MMC)
The control and intermediate results of these instructions re-
side in registers and memory; thus, the instruction can be
interrupted between the completion of one iteration (oper-
and execution cycle) and the point in time (during the next
iteration) when a memory location or register is modified.
If
an interrupt occurs during this time, the current iteration
is aborted and the instruction address portion of the program
status doubleword remains pointing to the interrupted instruc-
tion. After the interrupt-servicing routine is completed, the
instruction continues from the point at which it was inter-
rupted and does not begin anew.
SINGLE-INSTRUCTION INTERRUPTS
A s ingle- instruction interrupt is a situation where an interrupt
level is activated, the current program is interrupted, the single-
instruction in the interrupt location is executed, the interrupt
level is automatically cleared and armed, and the interrupted
program continues without be ing disturbed or delayed (except
for the time required for the singl e-instruction).
If any of the following instructions is executed in any in-
terrupt location, then that interrupt automaticall y becomes
a single-instruction interrupt.
Instruction Name
Modify and Test Byte
Modify and Test Halfword
Modify and Test Word
Mnemonic
MTB
MTH
MTW
The modify and test instruction modifies the effective byte,
halfword, or word (as described in the section "Fixed-point
Arithmetic Instructions") but the current condition code re-
mains unchanged (even if overflow occurs). The effective
address ofa modify and test instruction in an interrupt loca-
tion (except counter 4) is always treated as an actual
address, regardless of whether or not the memory map is
currently being used. Counter 4 uses the mapped location if
map is currently invoked in the PSD.
The execution of a
modify and test instruction in an interrupt location, including
mapped and unmapped counter 4,
is independent of the
memory access protection codes and the write-protection
locks; thus, a memory protection violation trap cannot
occur (a nonexistent memory address wi II cause an unpre-
dictable operation).
Also, the fixed-point overflow trap
cannot occur as the result of overflow caused by executing
MTH or MTW in an interrupt location.
The execution of a modify and test instruction in an interrupt
location automatically clears and arms the corresponding in-
terrupt level, allowing the interrupted program to continue.
22
Trap System
When a modify and test instruction is executed in a count-
pulse interrupt location, all of the above conditions
appl~
in addition to the following: If the resultant value in the
effective location is zero, the corresponding counter-
equals-zero interrupt is triggered.
TRAP SYSTEM
When a condition that is to result in an interrupt is
sensed, a signal is sent to an interrupt level.
If that
level is "armed" it advances to the waiting state. When
all of the conditions for its acknowledgment have been
achieved, the interrupt level eventually advances to the
active state, where it finally causes the computer to take
an instruction from a specific location in memory.
The com-
puter may execute many instructions between the time that
the interrupt requesting condition is sensed and the time that
the actual interrupt acknowledgment occurs.
However, de-
tecting any of the conditions listed in Table 3 results in a
trap (the immediate execution of the instruction in a unique
location in memory).
When a trap condition occurs, the CPU sets the trap state. De-
pending on the type of trap, the instruction currently being exe-
cuted by the CPU mayor may not be carried to completion. In
I
any event, the instruction is terminated with a trap sequence.
~
In this
sequ~nce,
the instruction address (IA) portion of the
program status doubleword (PSD), which has already been
incremented by 1, is decremented by 1 and then the instruc
tion in the location associated wi th the trap is executed.
An interrupt acknowledgment cannot occur unti
I
the execu-
tion of the instruction in the trap location is completed. The
instruction in the trap focation must be an XPSO instruction;
if the execution of any other instruction in a trap location
is attempted as the resul t of a trap activation, the results of
the instruction are unpredictable. The detai led operation of
XPSD is described in Chapter 3,
II
Control Instructions".
The XPSO instruction in a trap location is accessed without
using the memory map, regardless of whether or not the mem-
ory map is in effect when the trap condition occurs.
Also,
no memory protection violation or privileged instruction
violation can occur as a result of either accessing or exe-
cuting an XPSO instruction in a trap location. Table 3
summarizes the description of the trap system.
NONALLOWED OPERATION TRAP
The occurrence of one of the nona II owed operations always
causes the computer to abort the instruction being exe-
cuted (at the time that the nona II owed operation is detected)
and to immediately execute the instruction in trap location
X'40'.
NONEXISTENT INSTRUCTION
Any instruction that is neither standard nor optional on
SIGMA 6 is defined as nonexistent (this incl udes immediate
addressin"g instructions that are indirectly addressed).
If
execution of a nonexistent instruction is attempted, the
computer traps to location X '
40 '
at the time the instruction
is decoded.
The operation of the XPSD instruction in trap
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