Xerox Sigma 6 Reference Manual page 84

These conditions are summarized in the truth table shown
below. General information on memory addressing is con-
tained in Chapter2 under "Memory Control Storage", "Mem-
ory Reference Addresses", and IIMemory Address Control II.
XPSD 10
PSD9
XPSD Address Type Map?
1
Ind. Ref. Addr.
yes
1
Effect. Addr. yes
0
Ind. Ref. Addr. no
Effect. Addr. no
1
Ind. Ref. Addr. no
I
yes t
0
Effect. Addr.
no
0
Ind. Ref. Addr. no
Effect. Addr. no
tllYes li only if XPSD not executed in an interrupt or
trap location.
The current program status doubleword is stored in the double-
word location pointed to by the effective address of XPSD
in the following form:
The current program status doubleword is replaced by a new
program status doubleword as follows:
1.
The effective address of XPSD is incremented by 2, so
that it points to the next doubleword location. The ad-
dress thus generated is subject to the same mapping con-
sideration as the original effective address {i.e., mapping
is performed with the new address if bit 10 of XPSD is
,a 1 and bit 9 of the current program status doubl eword
is also a 1; otherwise, mapping is not performed}. The
contents of the next doubleword location are referred
to as the second effective doubleword, or ED2.
2. Bits 0 through 35 of the current program status double-
word are unconditionally replaced by bits 0 through 35
of the second effective doubl eword. The affected por-
tions of the program status doubleword are:
Bit
Position Designation Function
0-3
CC Condition code
5-7
FS, FZ, FN Floating control
8 MS Master/slave mode control
9 MM Mapping mode control
10 DM Decimal arithmetic trap mask
11
AM Fixed-point arithmetic trap mask
15-31 IA Instruction address
34-35 WK 'Write key
3. A logical inclusive OR is performed between bits 37
through 39 of the current program status doubleword
76 Control Instructions
and bits 37 through 39 of the second effective double-
word.
Bit
Position Designation Function
37
CI
Counter interrupt inhibit
38
II
VO
interrupt inhibit
39 EI External interrupt inhibit
If any (or all) of bits 37, 38, or 39 of the second effec-
tive doubleword are OIS, the corresponding bits in the
current program status doubleword remain unchanged;
if any (or all) of bits 37, 38, or 39 of the second effec-
tive doubleword are ]Is, the corresponding bits in the
current program status doubl eword are set to lis. See
page 19 for a detai
I
ed discussion of the interrupt inhibits.
4. If bit position 8 (LP) of XPSD contains a I, bits 55-59 of
the current program status doubleword (register pointer)
are replaced by bits 55 through 59 of the second effec-
tive doubleword; if bit 8 of XPSD is a 0, the current
register pointer value remains unchanged.
The following additional operations are performed on the new
program status doubleword if, and only if the XPSD is being
executed as the result of a nonallowed operation (trap to lo-
cation X'40') or a call instruction (trap to location X'48',
X
1
49
1
,
X'4A', or XI4BI):
1.
Nonallowed operations - the following additional func-
tions are performed when XPSD is being executed as a
resul t of a trap to location X
1
40
1
:
a. Nonexistent instruction - if the reason for the trap
condition is an attempt to execute a nonexistent in-
struction, bit position 0 of the new program status
doubleword (CC I) is set to 1. Then, if bit 9 (AI)
of XPSD is a I, bit positions 15-31 of the new pro-
gram status doubleword (next instrucHon address)
are incremented by 8.
b. Nonexistent memory address - if the reason for the
trap condition is an attempt to access or write into
a nonexistent memory region, bit position 1 of the
new program status doubl eword (CC2) is set to 1.
Then, if bit 9 of XPSD is a I, the instruction ad-
dress portion of the new program status doubl eword
is incremented by 4.
c. Privileged instruction violation - if the reason for
the trap condition is an attempt to execute a privi-
leged instruction while the computer is in the slave
mode, bit position 2 of the new program statusdouble-
word (CC3) is set to
1.
Then, if bit position 9 of
XPSD is 1, the instruction address portion of the new
program status doubleword is incremented by 2.
d. Memory protection violation - if the reason for the
trap condition is an attempt to read from or write into
a memory reg ion to wh i ch the program does not have
proper access, bit position 3 of the new program status
doubleword (CC4) is set to
1.
Then, if bit 9 of XPSD
is a 1, the instruction address portion of the new
program status doubleword is incremented by
1.