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RD
READ DIRECT
(Word index alignment, privileged)
The CPU is capable of directly communicating with other
elements of the SIGMA 6 system, as well as performing in-
ternal control operations, by means of the READ DIRECT/
WRITE DIRECT (RD/WD) lines.
The RD/WD lines consist
of 16 address lines, 32 data lines, 2 condition code lines,
and various control lines, that are connected to various
CPU circuits and to special systems equipment.
READ DIRECT causes the CPU to present bits 16 through 31
of the effective virtual address to other elements of the
SIGMA 6 system on the RD/WD address lines.
Bits 16-31
of the effective virtual address identify a specific element
of the SIGMA 6 system that is expected to return informa-
tion (2 condition code bits plus a maximum of 32 data bits)
to the CPU. The significance and number of data bits re-
turned to the CPU depend on the selected element.
If
the
R field of RD is nonzero, up to 32 bits of the returned data
are loaded into genera I register R; however, if the R field
of RD is 0, the returned data is ignored and genera I regis-
, . ter 0 is not changed.
The condition code is set by the ad-
dressed element, regardless of the value of the R field.
Bits 16-19 of the effective virtual address of RD determine
the mode of the RD instruction, as follows:
Bit Position
16
17
18
19
Mode
0 0 0
o
0
0
o
0
1
o
0
1
o
Internal computer control
1
Unassigned
o
XDS testers
1 } Assigned to various groups of standard
XDS products
o
1
Spec ial systems control (for customer use
with specially designed equipment)
If bits 16-19 of the effecti ve vi rtua I address are nonzero
(mode 1 through mode F), CC 1 and CC2 are set to zero and
CC3 and CC4 are set according to the state of the two con-
dition code I ines from the external device.
READ DIRECT INTERNAL COMPUTER CONTROL (MODE 0)
In this mode, the condition code is unconditionally set ac-
cording to the states of the four SENSE switches on the pro-
cessor control panel.
If
a particular SENSE switch is set,
the corresponding bit of the condition code is set to 1; if a
SENSE switch is reset, the corresponding bit of the condi-
tion code is set to
0
(see "SENSE" in chapter
5).
READ SENSE SWITCHES
The following configuration of RD can be used to read the
control panel SENSE switches:
In th is case, only the condition code is affected.
80
Control Instructions
READ AND RESET MEMORY FAULT INDICATORS
Each core memory module is associated with a MEMORY FAULT
indicator that is turned on whenever a memory parity or over-I
temperature condition occurs.
The following configuration
of RD is used to record and reset the MEMORY FAULT indi-
cators.
If the R field of RD is nonzero, bit positions 0-23 of register
R are reset to all O·s, bit positions 24-31 are set according
to the current states of the MEMORY FAULT indicators, and
all MEMORY FAULT indicators are reset. If a bit position
in register R is set to 1, a memory fault has been detected
in the corresponding core memory module. If the R field of
RD is 0, the MEMORY FAULT indicators and the contents
of register 0 remain unchanged (although the condition code
is still set to the value of the SENSE switches).
The MEM-
ORY FAULT indicators are also reset by means of the SYS
RESET/CLEAR switch on the processor control panel.
Affected: (R),CC,MEMORY FAULT Indicators
WD
WRITE DIRECT
(Word index
01
ignment, privileged)
WRITE DIRECT causes the CPU to present bits 16 through 31
of the effective virtual address to other elements of the SIG-
MA
6 system on the RD/WDaddress lines(see READ DIRECT).
Bits 16-31 of the effective virtua I address identify a specific
element of the SIGMA 6 system that is to receive control in-
formation from the CPU. If the R fie Id of WD is nonzero,
the 32-bit contents of register R are transmitted to the speci-
fied element on the RD;WD data lines. If the R field of
WD is 0, 32 O·s are transmitted to the specified element (in-
stead of the contents of register 0). The condition code is
I
set by the addressed element, regardless of the value of the
R field.
Bits 16-19 of the effective virtual address determine the
mode of the WD instruction, as follows:
Bit Position
16
17
18
0 0 0
0 0 0
o
0
1
0 0 1
19
Mode
o
1
o
1
o
Internal computer control
Interrupt control
XDS testers
}
ASSigned to various groups of standard
XDS products
1
Special systems control (for customer use
with specially designed equipment)
If bits 16-19 of the effective virtual address are nonzero
(mode 1 through mode F), CC 1 and CC2 are set to zero and
CC3 and CC4 are set according to the state of the two con-
dition code lines from the external device.
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