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EXU
EXECUTE
\.Word index alignment)
EXECUTE causes the computer to access the instruction in
the location pointed to by the effective address of EXU and
execute the subject instruction. The execution of the sub-
ject instruction, including the processing of trap and in-
terrupt conditions, is performed exactly as if the subject
instruction were initially accessed instead of the EXU in-
structi on.
If the subj ect instruction is another EXU, the
computer executes the subject instruction pointed to by the
effective address of the second EXU as described above.
Such "chains" of EXECUTE instructions may be of any length,
and are processed (without affecting the updated instruction
address) until an instruction other than EXU is encountered.
After the final subject instruction is executed, instruction
execution proceeds with the next instruction in sequence
after the initial EXU (unless the subject instruction is an
LPSD or XPSD instruction, or is a branch instruction and
the branch condition is satisfied).
If
an interrupt activation occurs between the beginning of
an EXU instruction (or chain of EXU instructions) and the
last interruptible point in the subject instruction, the com-
puter processes the interrupt-servicing routine for the ac-
tive interrupt
I
evel and then returns program control to the
EXU instruction (or the intial instruction of a chain of
EXU instructions), which is started anew. Note that a pro-
gram is interruptible after every instruction access, includ-
ing accesses made with the EXU instruction, and the inter-
ruptibility of the subject instruction is the same as the
normal interruptibility for that instruction.
If a trap condition occurs between the beginning of an EXU
instruction (or chain of EXU instructions) and the completion
of the subject instruction, the computer traps to the appro-
priate trap location.
The instruction address stored by the
XPSD instruction in the trap location is the address of the
EXU instruction (or the initial instruction of a chain of
EXU instructions).
Affected: Determi ned by
subject instruction
Traps: Determined by
subject instruction
Condition code settings: Determined by subject instruction
BCS
BRANCH ON CONDITIONS SET
(V%rd index alignment)
BRANCH ON CONDITIONS SET forms the logical product
(AND) of the R field of the instruction word and the current
condition code. If the logical product is nonzero, the
branch condition is satisfied and instruction execution pro-
ceeds with the instruction pointed to by the effective ad-
dress of the BCS
instru~tion.
However, if the logical
product is zero, the br:anch condition is unsatisfied and
instruction execution then proceeds with the next instruc-
tion in normal sequence.
Affected: (IA) if CC n RIO
If CC n (1)8_11 /0, EVA
15
_
31
--- IA
If
CC n (1)8-11
=
0, IA not affected
If the R field of BCS is
0,
the next instruction to be exe-
cuted after BCS is always the next instruction in ascending
sequence, thus effectively producing a "no operation"
instruction.
BCR
BRANCH ON CONDITIONS RESET
N'/ord index alignment)
BRANCH ON CONDITIONS RESET forms the logical pro-
duct (AND) of the
R
field of the instruction word and the
current condition code.
If the logical product is zero, the
branch condition is satisfied and instruction execution then
proceeds with the instruction pointed to by the effective ad-
dress of the BCR instruction.
However, if the logical pro-
duct is nonzero, the branch condition is unsatisfied and in-
struction execution then proceeds with the next instruction
in normal sequence.
Affected: (IA) if CC
n
R
=
0
If CC
n (1)8-11 = 0, EVA
15
_
31
-
IA
IF CC n (1)8-11
10,
IA not affected
If the R field of BCR is
0,
the 'next instruction to be execu-
ted after BCR is always the instruction located at the effec-
tive address of BCR, thus effectively producing a "branch
unconditional! y" instruction.
BIR
BRANCH ON INCREMENTING REGISTER
N'/ord index alignment)
BRANCH ON INCREMENTING REGISTER computes the
effective virtual address (EVA) and then increments the
contents of general regi ster R by
1.
If the resul t is a nega-
tive value, the branch condition is satisfied and instruction
execution then proceeds with the instruction pointed to by
the effective address of the BIR instruction.
However, if
the result is zero or a positive value, the branch condition
is not satisfied and instruction execution proceeds with the
next instruction in normal sequence.
Affected: (R), (IA)
(R) + 1 - R
If
(R)O
=
1,
EVA
15 - 31
- I A
If
(R)O
=
0, IA not affected
If
the effective address of BIR is unavailable to the slave
program for instruction access and the branch condition is
satisfied, or if the effective address of BIR is nonexistent,
Execute/Branch Instructions
73
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