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bit position contains a 1, and is not performed
if this bit position contains a 0.
Operation
This 7-bit field contains the code that desig-
nates the operation to be performed.
R
This 4-bit field designates any of the 16 regis-
ters of the current register block as an operand
source, result destination, or both.
x
Reference
address
This 3-bit field designates anyone of registers
1-7 of the current register block as an index
register. X =0 designates no indexing; hence,
register
°
cannot be used as an index register.
This 17-bit field contains the initial virtual ad-
dress of the instruction operand. Although the
contents of this field is always, in itself, a word
address, the reference address field allows any
word, doubleword, left halfword, or leftmost
byte within a word in memory to be directly
addressed. Halfword and byte operations re-
quire additional address bits for halfwords and
bytes that do not begin on a word boundary.
Thus, to address the second halfword of a word,
the X fi~ld of the instruction must designate a
register that contains a 1 in its low-order bit
position. To address bytes 1, 2, or 3 of a word,
the X field of the instruction must designate a
register that contains 01, 10, or 11, respec-
tively, in its two low-order bit positions. See
II
Indexing and Index Registers" for a more com-
plete description of the SIGMA 6 indexing
process.
Some SIGMA 6 instructions are ofthe immediate-addressing
type.
The format of these instructions provides for an
operand within the instruction word itself, as shown below.
The functions of the Operation and R fields are identical to
those of the normal instruction format.
°
Operand
This bit position is shown coded with a 0 be-
cause indirect addressing cannot be used with
this type of instruction. If indirect addressing
is attempted, the computer treats the instruc-
tion as a nonexistent instruction.
This field contains an operand that is 20 bits in
I ength, with negative numbers represented in
two's-complement form.
There are several methods by which an instruction word
may specify the source of an operand or the destination of
a result. These methods are explained below.
IMMEDIATE OPERAND
The operation code of an i'mmediate operand instruction
spec
i
fi es that an operand is to be found in the operand
field (bit positions 12-31) of the instruction word itself,
12
Instructi on Format
and not in a general register or core memory location. The
operand field of this type of instruction cannot be modified
by indexing.
The following SIGMA 6. instructions are of
the immediate operand type:
Instruc ti on Name
Mnemonic
Page
load Immediate
LI
29
load Conditions and Floating
LCFI
32
Control Immediate
Add Immediate
AI
36
Mul tipl y Immediate
MI
38
Compare Immediate
CI
41
The byte string instructions are similar to those of the
. immediate operand type in that they cannot be modified
by indexing. However, the operand field of these in-
structions contains a byte address displacement (or a byte
address) that is a virtual address subject to modification by
the memory map. If an immediate or byte string instruction
is indirectl y addressed, it is treated as a nonexistent instruc-
tion by the computer.
MEMORY REFERENCE ADDRESSES
Core memory locations
°
through 15 are not accessible to
the
programm~r
because memory addresses
°
through 15 are
reserved as register designators for "register-to-register"
operations. Thus, an instruction can treat any register of
the current register block as if it were a location in core
memory.
Furthermore, the register block can be used to
hold an instruction (or a series of up to 16 instructions) for
execution just as jf the instruction (or instructions) were in
core memory.
The only restriction upon the use of the
register block for instruction storage is:
If an instruction accessed from a general register uses
the R field of the instruction word to designate the
next higher-numbered register and execution of the
instruction would alter the contents of the register so
designated, the contents of that register should not be
used as the next instruction in sequence because the
operation of the instruction in the affected register
would be unpredictable.
In the maximum core memory configuration (131,072 words),
memory addresses
II
wrap around" with address
°
(general
register 0) being the next consecutive memory address after
X I 1FFFFI(131,071). Core memory location 16 follows gen-
eral register 15 as the next location in ascending sequence.
Direct Reference Address. If neither indirect addressing
nor indexing is called for by the instruction, the reference
address field of the instruction is a direct reference address.
Indirect Reference Address. If indirect addressing is called
forbythe instruction (a 1 in bit position 0 of the instruction
word), the reference address field is used to access a word
location that contains the direct reference address in bit
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