Xerox Sigma 6 Reference Manual page 49

Condition code settings:
o
2
o
1
3
o
o
1
4
o
1
o
Result in R
zero
negative
positive
no fi xed-poi nt overflow
fixed-poi nt overflow
no corry from bit position
0
corry from bit position
0
If
CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM)
is a 1, the computer traps to location X ' 43 1 after
loading the sum into register R; otherwise, the computer
executes the next instruction in sequence.
so
SUBTRACT DOUBLEWORD
(Doubleword index alignment)
SUBTRACT DOUBlEWORD forms the 64-bit twols comple-
ment of the effective doubleword, adds the complemented
doubleword to the contents of registers Rand Ru1 (treated
as a single, 64-bit register), loads the 32 low-order bits
of the sum into register Ru1 and loads the 32 high-or.der bits
of the sum into register R. R must be on even value; if R is
an odd value, the result in register R is unpredictable.
Affected: (R),(Rul),CC
-ED
+
(R, Ru1)--R, Ru1
Trap: Fixed-point overflow
Condition code settings:
o
2
o
i
3
o
o
4
o
1
o
Result in R, Ru1
zero
negative
positive
no fixed-point overflow
fixed-point overflow
no carry from bit position 0
carry from bit position 0
If
CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X I 43 1 after the
result is loaded into registers Rand Ru1; otherwise, the com-
puter executes the next instruction in sequence.
MI
MULTIPLY IMMEDIA TE
(Immediate operand)
The value field (bit positions 12-31 of the instructions word)
is treated as a 20-bit, twols complement integer. MUlTI-
PLY IMMEDIATE extends the sign of the value field (bit
position 12) of the instruction word 12 bit positions to the
left and multiplies the resulting 32-bit value by the con-
tents of register Ru 1, then loads the 32 high-order bits of
the product into register R, and then loads the 32 low-
order bits of the product into register Rul.
If
R is an odd value, the result in register R is the 32 low-
order bits of the product. Thus, in order to generate a 64-
bit product, the R field of the instruction must be even and
the multiplicand must be in register R+1. The conditioncode
settings are based on the 64-bit product formed duri ng in-
struction execution, rather than on the final contents of
register R. Overflow cannot occur.
Affected: (R), (Ru1), CC2, CC3, CC4
(Rul) x (1)12-31 SE - R, Ru1
Condition code setti ngs:
2 3 4 64-bit product
o o
zero
o
negative
o
positive
o
resul t is correct, as represented in reg-
ister Ru 1
result is not correctly representable in
register Ru
1
alone
If MI
is indirectly addressed, it is treated as a nonexistent
instruction, in which case the computer unconditionally
aborts execution of the instruction (at the time of opera-
tion code decoding) and traps to location X ' 40 ' with the
contents of register R, register Ru 1, and the condition code
unchanged; otherwi se, the computer executes the next i n-
struction° in sequence.
Example 1, even R field value:
Before executi on
(1)12-31 = X?OOOOI
(R)
xxxxxxxx
(Ru
1)
CC
X 110001000 1
xxxx
Example 2, odd R field value:
(1)12-31= X
1
01234
1
(R) X 1000300021
CC
xxxx
After execution
X?OOOOI
X 100007000 1
X?OOOOOOOI
xll 0
X ' 01234 1
X '369C2468I
xOlO
MH MULTIPLY HAlFWORD
(Halfword index al ignment)
MULTIPLY HALFWORD multiplies the contents of bit posi-
tions 16-31 of register R by the effective halfword (with
both halfwords treated as signed, twols complement inte-
gers) and stores the product in register Ru1 (overflow can-
not occur).
If
R is an even value, the original multiplier
in register R is preserved, allowi ng repetitive halfword
multiplication with a constant multiplier; however, if R is
Fixed-Point Arithmetic Instructions
41