Summary Of Sigma 6 Trap System - Xerox Sigma 6 Reference Manual

Table 3. Summary of SIGMA 6 Trap System
Location
Dec. Hex. Function
PSD
Mask Bit
64
65
66
67
68
69
70
72
73
74
75
76
40
41
42
43
44
45
46
48
49
4A
4B
4C
79 4F
Nonallowed operation
1. Nonexistent instruction
2. Nonexistent memory
address
3. Privileged instruction
in slave mode
4.
Memory protection
Unimplemented instruction
Push-down stac k lim it
reached
Fixed-point arithmetic
overflow
Floating-point fault
none
none
TW, TSt
AM
1. Characteristic overflow none
2. Divide by zero
3. Significance check
Decimal arithmetic fault
Watchdog timer runout
CALL
1
CALL 2
CALL 3
CALL 4
Reserved
none
FS, FZ,
FN
DM
none
none
none
none
none
Time of Occurrence
Instruction decoding
Prior to memory access
Instruction decoding
Prior to memory access
Instruction decoding
At the time of stack limit
detection
Spec ial Action During XPSD
Set CCl after new CC is
loaded from memory. If bit
9 of XPSD is 1, add 8 to
the new instruction address
value loaded from memory.'
Set CC2 after new CC is
loaded from memory.
If bit
9 of XPSD is 1, add 4 to
the new instruction address
value loaded from memory.
Set CC3 after new CC is
loaded from memory.
If bit
9 of XPSD is 1, add 2 to
the new instruction address
value loaded from memory.
Set CC4 after new CC is loaded
from memory.
If
bit
9
of XPSD is
1,
add
1
to the new instruction
address value loaded from memory.
none
none
For al
I
instructions except DW none
and D H, trap occurs after com-
pletion of instruction. For DW
and D
H,
instruction is aborted
with memory, regi sters, CC 1,
CC3, CC4 unchanged.
At time of fault detection; the
condition code is set to indi-
cate the reason for the trap
At time of fault detection; the
condition code is set to indi-
cate the reason for the trap
At time of runout
Instruction decoding
Instruction decoding
Instruction decoding
Instruction decoding
none
none
none
The R fi el d of the CA LL i nstruc-
tion is ORed into new CC set-
tings loaded from memory.
If
bit 9 of XPSD is 1, the R field
of the CALL instruction is ad-
ded to the new instruction ad-
dress value loaded from memory.
~ _ _ ~~ _ _ ~ _ _ _ _ _ _ ~~ _ _ _ _ _ _ _ _ _ _ _ _ ~ _ _ _ _ _ _ _ _ _ _ L ' . _ _ _ • _ _ _ _ _ • _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
tThe TW and TS mask bits are contained within the stack pointer doubleword for each push-down stack.
T rap System 23