Xerox Sigma 6 Reference Manual page 66

2 3
4
Result in DECA
a a a a
zero
} no illegal digit or sign
a
0
a
negative
detected, i nstructi on
a a a
positive
completed
DO DECIMAL DIVIDE
(Byte index
al
ignment, continue after interrupt)
If there is no illegal digit or sign in the
effe~tive
deci-
mal
operand and if there is at
least
one
decimal
sign in
the dec
imal
accumulator, DECIMAL DIVIDE divides the
contents of the decimal accumulator (dividend) by the ef-
fective decimal operand (divisor). Then, if no overflow
has occurred, the computer
loads
the quotient (15 decimal
digits plus sign) into the 8 low-order bytes of the decimal
accumulator (registers 14 and 15), and loads the remainder
(also
15 decimal digits plus sign) into the 8 high-order bytes
of the dec
imal
accumulator (registers 12 and 13). The sign
of the remai nder is the same as that of the
original
dividend.
If the quotient is zero, the sign of the quotient is forced to
the positive form.
Overflow can occur if any of the following conditions are
not satisfied before the initial execution of DECIMAL
DIVIDE:
1. The divisor must not be zero.
2. The length of the divisor must not be greater than 15
decimal digits (i.e., the value of L must not exceed 8.)
3.
If the length of the dividend is greater than 15 decimal
digits, the absolute value of the significant di gits to
the left of the 15th digit position (i.e., those digits in
registers 12 and 13) must be less than the absolute value
of the divisor.
This instruction can be interrupted during the course of its
execution, and can then be resumed without producing an
erroneous result (provided that the contents of the decimal
accumulator are not altered between interruption and con-
tinuation).
Actually,
the instruction is reexecuted, but
since there is no initializing phase, it begins with the same
iteration that was started prior to the interrupt.
Affected: (DECA), CC
(DECA)';- EDO - DECA
Traps:
Decimal
arithmetic
Condition code settings:
2 3 4 Result in DECA
a
illegal digit or
I
sign detected
instruction aborted
a
overflow
a a a a
zero quotient
}
no illegal digit or
a
0
a
negative quotient
sign detected, no
overflow, instruc-
a
0 0 positive quotient tion completed
58 Decimal
Instructions
DC DECIMAL COMPARE
(Byte index al ignment)
If there is no illegal digit or illegal sign in the effective
decimal operand or in the decimal accumulator, DECIMAL
COMPARE expands the effective decimal operand to 16
bytes (31 digits plus sign) by appending high-order
OIS,
al-
gebraical
Iy
compares the expanded decimal number to the
contents of the entire dec imal accumulator, and sets CC3
and CC4 according to the result of the comparison (a posi-
tive zero compares equal to a negative zero).
Affected: CC
(DECA) : EDO
Traps: Decimal arithmetic
Condition code settings:
2 3
4 Result of comparison
a
illegal digit or sign detected, instruction
aborted
0
a
0 0
(DECA) equals EDO
I
no
illegal
digit
0 0
a
(DECA) less than EDO or sign detected,
0 0 0 (DECA) greater than
instruction com-
EDO
pleted
DSA
DECIMAL SHIFT ARITHMETIC
(Byte index alignment)
Reference address
If no illegal digit or sign is detected in the decimal accu-
mulator, DECIMAL SHIFT ARITHMETIC arithmetically shifts
the contents of the decimal accumulator (excluding the
decimal sign), with the direction and amount of the shift
determined by the effective virtual address of the instruc-
tion.
If the result in the decimal accumulator is zero, the
resulting sign remains unchanged.
If no indirect addressing or indexing is used with DSA, the
shift count C is the contents of bit positions 16-31 of the
instruction word. If only indirect addressing is used with
DSA, the shift count is the contents of bit positions 16-31
of the word pointed to by the indirect address in the
instruction word.
If indexing only is used with DSA, the
shift count is the contents of bit positions 16-31 of the
instruction word plus the contents of bit positions 14-29
of the designated index register (bits 0-13, 30, and 31 of
the index are ignored).
If
indirect addressing and indexing
are both used with DSA, the shift count is the sum of the
contents of bit positions 16-31 of the word pointed to by
the indirect address and the contents of bit positions 14-29
of the designated index register.
The shift count, C, is treated as a 16-bit signed binary in-
teger, with negative integers in twols complement form.
If the shift count is positive, the contents of the decimal
accumulator are shifted left C decimal digit positions; if
the shift count is negative, the contents ::If the decimal