Tait TM8100 mobiles Service Manual page 95

Figure 3.14 Block diagram of the digital board (TM8100 radios)
Trans- DIG TX INH
mitter
DIG SYN EN
SYN LOCK
DIG SYN TR SW
Fre-
DIG SYN FAST
quency
DIG SYN LATCH
Synthe-
SYN DIG FREF
sizer
DIG SYN SPI DO
DIG SYN SPI CLK
DIG RX LE
RX DIG LD
Receiver
DIG RX NB EN
DIG RX EN
CDC2 DIG SDTO
DIG CDC2 SDTI
DIG CDC2 SCLK
DIG CDC2 LRCK
DIG DAC SPI DO
DIG DAC SPI CLK
DIG DAC LATCH
DIG CDC ARSM
CDC DIG VSFS
CDC DIG VSDO
DIG CDC VSDI
CDC DIG BSOFS
CDC DIG BSDO
DIG CDC ASFS
DIG CDC ASDI
CDC DIG ASDO
CODEC
DIG CDC RST
and
Audio
DIG SYS CLK
DIG AUD PA EN1
DIG AUD PA EN2
+1V8
Signal Types:
RF
analog
clock
digital
asynchronous serial data
synchronous serial data
TM8100/TM8200 Service Manual
© Tait Electronics Limited November 2007
DIG EE CS
EE DIG SPI DI
Digital Board
FPGA
McBSP0 (x4)
McBSP1 (x4)
System
Clock
BIRDIE
FPGA CLK
+1V5 1V5
Regulator
PSU SYS RST
FPGA JTAG Signals:
FPGA JTAG TCK
FPGA JTAG TMS
FPGA JTAG TDO
JTAG FPGA TDI
Factory Connector
DGND
Serial
EEPROM
AGND
DIG CH SPI CLK
DIG CH SPI DO
ITF CH SPI DI
DIG CH LE
ITF CH GPI1
DIG CH GPO1
ITF CH PTT
ITF CH HOOK
ITF ON OFF
ITF IOP GPIO1-7
DIG IOP TXD
ITF IOP RXD
ITF AUX GPI1-7
DIG AUX GPO4-7
DIG AUX TXD
ITF AUX RXD
DIG CH TXD
ITF CH RXD
DIG TX EN
RAM
Flash
Memory
DIG PSU LATCH
DIG WD KICK
DIG SLP EN
DSP and
Address
Decoder
1V8
Regulator
+1V8 +3V3
PSU SYS RST
DIG RX EN
DSP JTAG Signals:
DSP JTAG TCK DSP JTAG TRST
DSP JTAG TMS DSP JTAG EMU0
DSP JTAG TDO DSP JTAG EMU1
JTAG DSP TDI
+3V3
AGND
Circuit Descriptions
Interface
Power
Supply
95