Tait TM8100 mobiles Service Manual page 50

Figure 2.15 Software architecture (radio with graphical-display control head shown)
Serial Flash
Flash Memory
RISC Proc.
FPGA Image
FPGA
Dynamic
Memory
Software Start-Up
50 Description
FPGA Image
RISC Processor
Boot Code
Radio Application
Custom Logic
Additional Digital
Signal Processing
When the radio is turned on, the following processes are carried out on the
main board:
Note
This process describes the software start-up into normal radio
operation mode.
1. The FPGA image, which includes the RISC processor and the cus-
tom logic, is loaded from the serial flash to the FPGA.
2. The RISC processor executes the boot code, which carries out an
initialization and auto-calibration, and—in the case of a fault—
generates an error code for display on the control head.
3. Normal radio operation starts with:
the RISC processor executing the radio application code,
■
including application software
the DSP executing the DSP code for processing of digital signals
■
the custom logic executing additional digital signal processing.
■
FPGA
Radio Application Code
Code
© Tait Electronics Limited November 2007
Serial Flash
FPGA Image
Flash Memory
Boot Code
Database
DSP Code
DSP
DSP Code
SRAM
Dynamic Memory
TM8100/TM8200 Service Manual