Lvds Interface; Table 3-8. Lvds Interface Pin/Signal Descriptions (J8) - ADLINK Technology CoreModule 730 Reference Manual

Chapter 3
Table 3-7. VGA Interface Pin Signals (J7) (Continued)
9 VSYNC
10 PWR
11 DDC_DATA
12 DDC_CLK
Note: The shaded areas denote power or ground.

LVDS Interface

Table 3-8 describes the pin signals of the LVDS interface, which uses a 20-pin, right-angle header with 2
rows, odd/even sequence (1, 2), and 0.079" (2mm) pitch.

Table 3-8. LVDS Interface Pin/Signal Descriptions (J8)

Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Note: The shaded areas denote power or ground.
22
Vertical Sync – This signal is used for the digital vertical sync output to
the CRT.
Power – Provided through fuse (F1) to +5 volts +/- 5%. F1 is next to J7
header on board.
Display Data Channel - Data
Display Data Channel - Data
Signal
VCC_INTRV
VCC_LVDS_CONN
GND
GND
LVDS_CLK+
LVDS_CLK-
LVDS_DAT3+
LVDS_DAT3-
LVDS_DAT2+
LVDS_DAT2-
LVDS_DAT1+
LVDS_DAT1-
LVDS_DAT0+
LVDS_DAT0-
LVDS_BKLT_CTRL
LVDS_VDD_EN
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_BKLT_EN
NC
Reference Manual
Description
+12V source
JP2 = +3.3 or +5V source
Ground
Ground
Clock Positive Output
Clock Negative Output
Data 3 Positive Output
Data 3 Negative Output
Data 2 Positive Output
Data 2 Negative Output
Data 1 Positive Output
Data 1 Negative Output
Data 0 Positive Output
Data 0 Negative Output
Backlight Control
LCD Enable
Clock
Data
Backlight Enable
Not connected
Hardware
Line
Gnd
Clk
3
2
1
0
CoreModule 730