Cpu; Graphics; Memory; Interrupt Channel Assignments - ADLINK Technology CoreModule 730 Reference Manual

Chapter 3

CPU

The CoreModule 730 offers an embedded microprocessor—the Intel Atom Z530—operating at 1.6 GHz.
This CPU provides a powerful x86 core and support for the SCH (System Controller Hub) US15W which
integrates Northbridge and Southbridge functions.

Graphics

The US15W SCH integrates a graphics controller which provides LVDS and SDVO ports that terminate to
LVDS and VGA headers, respectively. The graphics controller achieves high 2D and 3D performance with a
DDR2 memory interface (shared with the system controller) supporting a bandwith of up to 2 GB (DDR2 @
up to 533 MHz.)

Memory

The CoreModule 730 provides one 200-pin DDR2 SODIMM of up to 2GB of SDRAM memory, which is
shared between the system memory controller and the graphics memory controller in the SCH.

Interrupt Channel Assignments

The interrupt channel assignments are shown in

Table 3-1. Interrupt Channel Assignments

Device vs IRQ No.
Timer
Keyboard*
Secondary Cascade
COM1*
COM2*
COM3*
COM4*
Parallel*
RTC
IDE
Math Coprocessor
PS/2 Mouse*
PCI INTA*
PCI INTB*
PCI INTC*
PCI INTD*
PCI INTE
PCI INTF
PCI INTG
PCI INTH
Legend: D = Default, O = Optional, X = Fixed, * = Located on the optional expansion module.
NOTE
16
Table
0 1 2 3 4
X
X
X
O D
D O
O O
O O
The PCI IRQs for the Ethernet, Video, and Internal Local Bus are automatically
assigned by the BIOS Plug and Play logic. Local ISA IRQs assigned during
initialization can not be used by external devices.
Reference Manual
3-1.
5 6 7 8 9 10
O
O
O
D
O D
X
Automatically Assigned
Automatically Assigned
Automatically Assigned
Automatically Assigned
Automatically Assigned
Automatically Assigned
Automatically Assigned
Automatically Assigned
Hardware
11 12 13 14 15
O
O
D
O
O O
D
X
X
CoreModule 730